Stmicroelectronics S.r.l.

Sgs-thomson Microelectronics S.r.l.

Politecnico Di Milano

Other

Micron Technology Incorporated

Aldo Losavio

Giovanni Campardo

Rino Micheloni

Gian Pietro Vanalli

Pier Paolo Stoppino

Paolo Pulici

Giuseppe Paolo Crisenza

Maurizio Bacchetta

Giorgio De Santi

Stefano Ricciardi

Roberto Dossi

A substrate has a first surface and a second surface opposed to each other. A blind hole is formed in the substrate extending from the first surface at a location for each through via. Each blind hole is filled with a conductive filler; a deepest part of each filler forming a bump portion made of a solder material. Part of the substrate extending from the second surface is removed to have at least the bump portions protrude from the substrate. The non-protruding part of each filler defines the corresponding via and the bump portion defines the corresponding solder bump.

Through via structure including a conductive portion and aligned solder portion

A method for manufacturing solder bumps for through vias in a substrate having a first surface and a second surface opposed to each other. The method includes the steps of forming a blind hole extending in the substrate from the first surface for each via and filling each blind hole with a conductive filler; a deepest part of each filler includes a bump portion made of a solder material. The method further includes the step of removing a part of the substrate extending from the second surface to have at least the bump portions protrude from the substrate. The non-protruding part of each filler defines the corresponding via and the bump portion defines the corresponding bump.

Method for forming bumps in substrates with through vias

An electronic system adapted to perform a corresponding function and including at least a first subsystem and a second subsystem, the first subsystem and the second subsystem being operatively couplable to each other through a plurality of electric connections to perform the function of the system, in which the first subsystem and the second subsystem are respectively integrated on a first material chip and on a second material chip, the plurality of electric connections including a plurality of conductive through holes formed in at least one of the first and second chips and adapted to form a corresponding plurality of inter-chip electric connections when the first and the second chips are superimposed.

Multi chip electronic system

An integrated electronic device includes at least one supply pin and at least one booster coupled to said at least one supply pin. Moreover, there is at least one integrated circuit powered by the at least one booster and associated therewith in a 'system in a package configuration.'

Integrated electronic device having a low voltage electric supply

The memory device has a memory block, formed by a plurality of standard sectors and a redundancy portion; a control circuit, which controls programming and erasing of the data of the memory cells; and a correctness verifying circuit for the data stored in the memory cells. The correctness verifying circuit is enabled by the control circuit and generates an incorrect-datum signal in the event of detection of at least one non-functioning cell. The control circuit moreover activates redundancy, enabling the redundancy portion and storing redundancy data in a redundancy-memory stage in response to detecting an incorrect datum. Various solutions implement column, row and sector redundancy, both in case of erasing and programming.

Self-repair method for nonvolatile memory devices with erasing/programming failure, and relative nonvolatile memory device

A self-repair method intervenes at the end of an operation of modification of a nonvolatile memory, selected between programming and erasing, in the event of detection of just one non-functioning cell, and carries out redundancy of the non-functioning cell. To this end, the memory array is divided into a basic portion, formed by a plurality of memory cells storing basic data, and into an in-the-field redundancy portion. The in-the-field redundancy portion is designed to store redundancy data that include a correct content of the non-functioning cell, the address of the non-functioning cell, and an activated redundancy flag. The redundancy is activated only after applying a preset maximum number of modification pulses and uses a redundancy replacement circuit and a redundancy data verification circuit.

Self-repair method for nonvolatile memory devices using a supersecure architecture, and nonvolatile memory device

The method for using a nonvolatile memory () having a plurality of cells (), each of which stores a datum, is based upon the steps of performing an modification operation of erasing/programming () the data of the memory; verifying () the correctness of the data of the memory cells; and, if the step of verifying () has revealed at least one incorrect datum, correcting on-th-field () the incorrect datum, using an error correcting code. The verification () of the correctness of the data is performed by determining () the number of memory cells storing an incorrect datum; if the number of memory cells storing the incorrect datum is less than or equal to a threshold (), the erroneous datum is corrected by the error correction code; otherwise, new erasing/programming pulses are supplied.

Self-repair method via ECC for nonvolatile memory devices, and relative nonvolatile memory device

A method for recovering the original properties of a silicon oxide film that has suffered a high energy implantation of dopants in the underlying silicon substrate, includes a brief heat treatment without causing an excessive lateral diffusion in the silicon substrate of the implanted dopants. Heat treating in an oven at a temperature of 800&deg; C. for few minutes per wafer, which was subjected to high energy implantation, makes it possible to recover etch rate characteristics that are practically similar to those of the original non-implanted silicon oxide.

Recovery of damages in a field oxide caused by high energy ion implant process

A planarization process for the manufacturing of highly-planar interlayer dielectric thin films in integrated circuits, particularly in non-volatile semiconductor memory devices, comprises the steps of: forming a first barrier layer over a semiconductor substrate wherein integrated devices have been previously obtained; forming a second layer of oxide containing phosphorous and boron over the first undoped oxide the concentration of boron being lower than the concentration of phosphorous; forming a third layer of oxide containing phosphorous and boron over the second oxide layer, the concentration of phosphorous being lower than or equal to the concentration of boron; performing a thermal process at a temperature sufficient to melt the third oxide layer, to obtain a planar surface.

Highly-planar interlayer dielectric thin films in integrated circuits

A method for measuring the degree of planarity in an integrated circuit includes depositing, onto a dielectric layer to be measured for planarity, a predetermined measure path of a conductive film and measuring the electric resistance of said measure path. The resistance of such a measure path is minimal where the surface on which it has been deposited is perfectly planar, and increases with the surface deviation from perfect planarity. An integrated circuit containing a measurement portion of conductive film and a reference portion of conductive film is described.

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Bergamo, Italy

Aldo Losavio