Deutsche Thomson-brandt Gmbh

Retina Implant Ag

Thomson Licensing

Albrecht Rothermel

Rainer Schweer

Roland Lares

Carlos Correa

Gunter Gleim

Heinrich Schemmann

Eberhart Zrenner

Martin Rieger

Gangolf Hirtz

David Gillies

John Stolte

Friedrich Rominger

Walter G Wrobel

Thomas Hollmann

Karin Rothermel

Phillppe Blaud

Walter-G Wrobel

An active retinal implant () to be implanted into an eye has an array () of stimulation elements () that emit stimulation signals to cells of the retina, wherein the stimulation elements () are designed as radiation-emitting elements.

Active retinal implant

An implantable device () is used to emit electrical stimulation signals to surrounding tissue by means of at least one stimulation electrode (). The device () has an input stage which is connected to a supply unit () by a cable, by means of which the input stage is supplied with at least one substantially square electrical AC voltage which is, averaged over time, at least virtually free of a DC voltage with respect to an external ground (), which can be connected to the tissue () (FIG.).

Implantable device

An implantable device () is used to emit electrical stimulation signals to surrounding tissue by means of at least one stimulation electrode (). The device () has a sensor unit (), which generates a useful signal (D) in the form of analogue voltage pulses () from externally fed signals, and an output stage () which generates the stimulation signals (E) from the useful signal (D). The output stage () emits the stimulation signals (E) in, averaged over time, a substantially DC voltage free fashion to an external ground (), which can be connected to the tissue ().

A method for obtaining line synchronization information items from a video signal is proposed. The inventive method is based on convolving the relevant part of an analogue video line signal with a pattern function. The result of the convolution operation is further processed to determine the time instants of the occurrence of the horizontal sync signals. The time instants are subsequently filtered to generate horizontal pulses. A video line memory allows to utilize subsequent horizontal sync signals for calculating the horizontal sync pulse of a current video line. The invention also relates to an apparatus for carrying out the method.

Method and apparatus for analyzing a digitally converted analogue signal

Method and device for arranging digitized image signals or data in orthogonal rows and columns

Method for obtaining line synchronization information items from a video signal, and apparatus for carrying out the method

Circuit for transmitting digital signals

A digital detector circuit for recovering the bit timing of a data stream with a PLL includes a digital phase detector and a digital pulse length detector whose output signals are added and integrated, and the result is used for controlling the oscillator frequency. The output signal of the pulse length detector is determined by a corresponding algorithm, one slow and two fast, with direction-dependent output signals of the pulse length detector being generated.

Digital detector circuit for recovering the bit timing from a data stream

An arrangement for reducing interference in tuned circuits in integrated circuits as a result of the reception and transmission of high frequencies. An external tuned circuit is integrated in the integrated circuit and the interference which is otherwise produced by the connecting pins is eliminated.

Arrangement for reducing interference in tuned circuits in integrated

A synchronizing signal separating circuit for a television receiver, comprising: a source of a video signal having a line synchronizing signal component; a line synchronizing signal component separator having an amplitude selective stage and having a flywheel stage imparting a response time constant to the separator which enhances noise immunity; a delay circuit for the video signal, for example a multiple line delay, coupled ,between the video signal source and the separator; a control circuit coupled to the video signal source and evaluating the time positions of line synchronizing pulses of a plurality of successive lines to identify a kind of line phase disturbance in which the line phase of an entire raster is displaced, the control circuit supplying a control signal to the separator indicative of the kind of phase disturbance; and, the flywheel stage being temporarily rendered inoperative responsive to the control signal, for example by temporarily decreasing the response time of the separator, upon identification of the kind of line phase disturbance in which the line phase of an entire raster is displaced. The control circuit may comprise: a second line synchronizing signal component separator; a phase comparator; a digital memory for phase deviations determined by the phase comparator; and, a counter for phase deviatons which generates the control signal upon reaching a predetermined number of phase deviations.

Synchronizing signal separating circuit with controlled flywheel stage

A control circuit for maintaining the mean value of the amplitudes of control pulses having a first level and data pulses having a second level includes a detector for providing the control pulses and the data pulses. A reference voltage source provides first, second and third reference voltages having three different levels. A plurality of comparators each receive both the control pulses and the data pulses. A first comparator also receives the lowest of the reference voltages and provides regulation pulses when the control pulses reach the level of the lowest reference voltage. A second comparator receives the second highest reference voltage and provides level limiting pulses to maintain the level of the regulation pulses constant. A third of the comparators receives the highest reference voltage and provides data pulses when the third reference voltage is reached.

Circuit arrangement for regulating signals

Delay chain oscillator having selectable duty cycle

A clocked digital signal processing system includes apparatus for unambiguously indicating the phase of an input signal relative to a reference clock signal. In particular, the disclosed apparatus reduces timing uncertainty between the reference clock, and the output signal of a phase detector representing the phase relationship between the input signal and the reference clock. A phase detector including a logic network provides plural comparison signals representing a phase relationship between the input and reference signals. The comparison signals are conveyed via first and second latch circuits, in respective groups, to a clocked downstream stage. The first and second latch circuits are clocked by different phases of the reference clock and provide outputs synchronous with the reference clock. The downstream stage responds to the reference clock for conveying output signals front the first and second latch circuits to an output at which the unambiguous indication appears.

System for unambiguously determining the phase of an input signal of

When processing a digital video signal, the problem often arises of converting the signal from a first sampling raster which is asynchronous with respect to the line interval to a second sampling raster which synchronous with the line interval. Interpolation filters are used for this purpose. The present invention provide a simple method for the conversion which does not require intermediate D/A or A/D conversion. For each line of the input signal, the phase of samples of the first sampling raster relative to the line synchronization pulse and the total number of the samples for this line are determined and are used to control of the interpolation filter.

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Neu-Ulm, Germany

Albrecht Rothermel