Infineon Technologies Ag

Siemens Aktiengesellschaft

Albrecht Mayer

Harry Siebert

Glenn Ashley Farrall

Frank Hellwig

Gerd Dirscherl

Patrik Eder

Viola Rieger

Laurent Heidt

Andreas Graefe

Andreas Kolof

Joerg Schepers

Klaus D McDonald-Maier

Thomas Kern

Michael Goessel

Wieland Fischer

Alexander Zeh

Simon Brewerton

Neil Stuart Hastie

Andreas Wenzel

Manuela Meier

Klaus Scheibert

Stefan Pfab

Sandeep Vangipuram

Witold Gora

Joerg Syassen

Martin Kaibel

Andreas Geiler

Sammy Baradie

Dietmar Konig

Reinhard Deml

Avni Bildhaiya

Wilhard Von Wendorff

Kajetan Nuernberger

Pawel Jewstafjew

Wolfram Carl

A device includes a safety domain having a processing unit and a memory and is configured to provide at least one functionality and to implement one more safety measures for detecting faults. The safety domain is configured to transmit at least one alarm signal indicating one or more detected errors in response to detecting the faults. The device further includes a security domain having a processing unit and a memory and is configured to provide cryptographic services and to obtain alarm signals. The security domain is configured to perform security-related operations in a secure state in response to obtaining an alarm signal from the safety domain.

Security device and methods of operating a security device

In various examples, a system on a chip is provided that is configured to be operated in a debug mode. The system on a chip includes a plurality of processor cores including a plurality of virtual machines and a further processor core, configured to, in the debug mode, initially execute first debug instructions after the system on a chip has started operating. The first debug instructions are configured to cause the further processor core to make a debug setting that, after the first debug instructions are executed, prevents a processor core executing second debug instructions from accessing at least one of the virtual machines and allows the processor core executing the second debug instructions to access at least one other of the virtual machines.

System on a chip and method for operating a system on a chip

A semiconductor chip includes an electronic hardware circuitry device that includes a plurality of partitionable hardware resources that each includes a corresponding resource allocation state. The electronic hardware circuitry includes a logic control circuit to control access to the plurality of hardware resources based on the respective resource allocation states of the hardware resources and based on input from one or more authorized agents. The semiconductor chip further includes a processor core to implement a plurality of software applications belonging to a first group or to a second group, each of the plurality of applications configured to access and interact with at least one corresponding hardware resource assigned to the respective application, implement assigning software agents each authorized and configured to cause the electronic hardware circuitry device to assign one or more unassigned hardware resources only to one or more of the software applications belonging to certain groups.

Systems, devices, and methods for dynamic allocation

A circuitry is disclosed having one or more circuits and a connector portion coupled that is to the one or more circuits. The connector portion includes a plurality of pins, at least some of the pins having assigned functionality, and wherein at least one first pin is to activate a mechanism to bring the one or more circuits into an electrically safe state. The circuitry is configured, in case the connector portion is coupled with a first connector in a first orientation, to allow the one or more circuits to operate properly via the connector portion. The circuitry is also configured so that in a case where the connector portion is coupled with a second connector in a second orientation different from the first orientation, the at least one first pin of the plurality of pins receives a reference potential that triggers activation of a safety mechanism.

Systems, devices, and methods for connectors

A method includes incrementing a counter with transmission of a process data from a first processor to a second processor, periodically decrementing the counter, if the counter is greater than a predetermined floor threshold value, wherein a period is a predetermined time interval; and stalling the first processor, if the counter is above a configurable load threshold value, so as to re-schedule the transmission of the process data from the first processor to the second processor.

Control system for process data and method for controlling process data

In different example embodiments, a system-on-chip is provided. The system-on-chip can have a control circuit with a plurality of control circuit areas, wherein the control circuit is configured to control a device, a security circuit which has a separately secured key memory and a hardware accelerator for cryptographic operations, wherein the security circuit is configured to electively enable either a read-only access or a read and write access to at least one of the control circuit areas, wherein the security circuit is furthermore configured to provide a communication path by means of the key memory and the hardware accelerator for the secured communication with a diagnostic system disposed outside the security circuit, to make the selection between the read access and the read and write access to the at least one selected area of the control circuit depending on a certificate supplied to the security circuit and authenticated by means of information stored in the key memory, and to execute the read access or the read and write access.

System-on-chip and method for operating a system-on-chip

A communication device is described including a receiver configured to receive a message including message data and a message authentication code, a first register for storing a received message authentication code and a second register for storing a computed message authentication code. The device also includes a first processor configured to extract the message authentication code from the message and to store the message authentication code in the first register, a second processor configured to compute a message authentication code based on the message data and to store the computed message authentication code in the second register, and a comparing circuit configured to compare the contents of the first register and the second register and to provide a comparison result. The device includes access control circuitry configured to prevent access by the second processor to the first register and to allow access by the first processor to the first register and to prevent access by the first processor to the second register and to allow access by the second processor to the second register.

Communication device and method for authenticating a message

Handling an exception includes (i) executing a return from an exception; and (ii) executing a subsequent instruction with an additional functionality in case the additional functionality of the subsequent instruction can be triggered by a special instruction.

Handling exceptions in a program

A System on Chip (SoC), including a plurality of processor cores including a secure master, which is configured to run security software, and a non-secure master, which is configured to run non-security software; a resource configured to be shared by the secure master and the non-secure master; and a state machine configured to protect the resource by allowing only the secure master to transition the resource to a particular state of the state machine, and allowing only the non-secure master to transition the resource to another particular state of the state machine.

Resource protection

A method includes invoking a first instruction that, when executed by a first processor, causes the first processor to perform a first operation, and that, when executed by the first processor, causes a second processor to perform a second operation. The method further includes a second instruction that, when executed by the first processor, causes the first processor to perform the first operation while causing the second processor to perform a third operation or while leaving the second processor unaffected. A control system includes a first processor and a second processor, wherein the first processor is configured to execute a first instruction to perform a first operation, wherein the second processor is configured to perform a second operation when the first processor executes the first instruction.

Control system and method of to perform an operation

A method of determining an access address includes determining a first address translation rule to translate a first input address to a first output address, determining a second address translation rule to translate a second input address to a second output address, and using at least one of the first address translation rule and the second address translation rule to determine the access address. An apparatus for accessing a memory based on a memory address includes a first address translator configured to translate a first input address to a first output address and a second address translator configured to translate a second input address to a second output address. The apparatus is configured to use at least one of the first address translator and the second address translator to translate the memory address to the access address.

Method and apparatus for use in accessing a memory

A method includes associating an associated processor address register with a predetermined operation, invoking an instruction including a reference to a referenced processor address register, and, if the referenced processor address register is the associated processor address register, performing the predetermined operation.

Control system and method of memory access

The disclosure proposes a circuit including a memory which has a multiplicity of memory cells, the memory having a first area and a second area, at least one memory cell comprising a part of the first area and a part of the second area, the first area having a lower reliability than the second area, and the circuit being set up in such a manner that first bits are stored in the first area and second bits are stored in the second area. A circuit for reading the memory and methods for writing to and reading the memory are also disclosed.

Memory having different reliabilities

A system for a multiple chip architecture that enables different system on-chip (SoC) systems with varying compatibilities to interact as one SoC via a transparent interface. The system address maps of the single SoCs are configured so that each provide a system address map of the two SoCs without overlap or address re-mapping when connected to one another via the transparent interface. The transparent interface enables components related to safety/security and interrupt communication of a first and second SoC within the multiple chip system to transparently communicate and interact. The transparent interface can enable sources of both SoCs to be flexibly mapped to interrupt services providers on the first/second SoC within the multiple chip system.

Growing community of inventors

Deisenhofen, Germany

Albrecht Mayer