Infineon Technologies Ag

Osram Opto Semiconductors Gmbh

Osram Oled Gmbh

Albrecht Kieslich

Matthias Lehr

Werner Graf

Hermann Sachse

Klaus Feldner

Norwin Von Malm

Siegfried Herrmann

Stefan Illek

Matthias Goldbach

Stephan Kudelka

Patrick Rode

Lutz Hoeppel

Johann Alsmeier

Dirk Offenberg

Herbert Benzinger

Markus Broell

Jürgen Faul

Christian Rumbolz

Detlef Weber

Thomas Schuster

Michael Huber

Bernd Boehm

Lothar Bauch

Jürgen Amon

Georg Rossbach

Thomas Zell

Jana Sommerfeld

Peter Thieme

Falko Höhnsdorf

Lars Voland

J&uuml;rgen Amon

Ralf Müller

Kevin Pears

Martin Herz

Sebastian Hoibl

The invention relates to a method for producing an optoelectronic semiconductor chip comprising the following steps: providing a semiconductor body () having a radiation-permeable surface (), and introducing structures () into the semiconductor body () on the radiation-permeable surface (), wherein the structures () are quasi-regular.

Method for producing an optoelectronic semiconductor chip having structures at the radiation passage surface, and optoelectronic semiconductor chip having structures at the radiation passage surface

A method of producing a plurality of optoelectronic semiconductor chips includes a) providing a layer composite assembly having a principal plane which delimits the layer composite assembly in a vertical direction, and includes a semiconductor layer sequence having an active region that generates and/or detects radiation, wherein a plurality of recesses extending from the principal plane in a direction of the active region are formed in the layer composite assembly; b) forming a planarization layer on the principal plane such that the recesses are at least partly filled with material of the planarization layer; c) at least regionally removing material of the planarization layer to level the planarization layer; and d) completing the semiconductor chips, wherein for each semiconductor chip at least one semiconductor body emerges from the semiconductor layer sequence.

Method of producing a plurality of optoelectronic semiconductor chips, and optoelectronic semiconductor chip

A method fabricates a semiconductor structure having a plurality of memory cells that are provided in a semiconductor substrate of a first conductivity type and contains a plurality of planar selection transistors and a corresponding plurality of storage capacitors connected thereto. The selection transistors have respective first and second active regions of a second conductivity type. The first active regions are connected to the storage capacitors and the second active regions are connected to respective bit lines, and respective gate stacks, which are provided above the semiconductor substrate in a manner insulated by a gate dielectric. In this case, a single-sided halo doping is effected, and an excessive outdiffusion of the halo doping zones is prevented by introduction of a diffusion-inhibiting species.

Method for fabricating a semiconductor structure

A method for the integration of field-effect transistors for memory and logic applications in a semiconductor substrate is disclosed. The gate dielectric and a semiconductor layer are deposited over the whole area both in the logic region and in the memory region. From these layers, the gate electrodes in the memory region are formed, the source and drain regions are implanted and the memory region is covered in a planarizing manner with an insulation material. Afterward, the gate electrodes are formed from the semiconductor layer and the gate dielectric in the logic region.

Method for fabricating a semiconductor product with a memory area and a logic area

A method for fabricating a trench structure, in particular a trench capacitor with an insulation collar, which is electrically connected to a substrate on one side via a buried contact. Fabrication includes, for example, providing a trench in the substrate using a hard mask with a corresponding mask opening; providing an at least partial trench filling; providing a liner on the resulting structure; carrying out an oblique implantation of impurity ions onto the liner for altering the etching properties of an implanted partial region of the liner; selectively removing the implanted partial region of the liner by a first etching for forming a liner mask from the complimentary partial region of the liner, which partially masks the top side of the trench filling; removing a part of the trench filling by a second etching using the liner mask; and replacing the removed part of the trench filling.

Method for fabricating a trench structure which is electrically connected to a substrate on one side via a buried contact

A method for reducing capacitative coupling between interconnects on a semiconductor structure includes producing a first insulating layer on a semiconductor substrate and etching trenches in the first insulating layer. Metallic interconnects are formed in the trenches by metallization. The semiconductor structure is polished to remove metal from the first insulating layer, leaving behind metal in the trenches. A portion of the first insulating layer between the first and second metallic interconnects is etched so that the first and second metallic interconnects project above the first insulating layer. A second insulating layer is applied on the substrate such that the metallic interconnects project into the second insulating layer. The second insulating layer has a relative permittivity that is lower than the relative permittivity of the first insulating layer.

Compact semiconductor structure

A mask for fabricating semiconductor components contains first transparent regions and second transparent regions. The second regions are laid out such that they do not act on the regions of the photoresist directly beneath them in the exposure of the photoresist through the mask. The transparent regions define a size and a shape of structures to be formed.

Mask for fabricating semiconductor components

A method for planarizing the surface of an isolating layer that is deposited on a semiconductor body is described. Zones where the isolating layer has a low level are covered with a block mask in order to be able to selectively etch zones of the isolating layer with a higher level.

Method for planarizing an isolating layer

A method of forming a bitline and a bitline contact and a dynamic random access memory (DRAM) cell array includes the following steps. The bitline and the bitline contact are formed in a two-step process, in which, first, the bitline contact is formed in a first dielectric layer and, then, the bitline of a conductive material having a lower resistivity than the bitline contact material is defined in a second dielectric layer ( ). According to a preferred embodiment, the second dielectric layer ( ) is made of a low k dielectric. The retention anneal process, which is usually performed in the standard DRAM process, is preferably made before depositing the bitline material and, optionally, the low k dielectric. A dynamic random access memory cell array having at least one bitline and a bitline contact can be manufactured by this method.

Method of forming a bitline and a bitline contact, and dynamic memory cell including a bitline and bitline made contact according to the method

In the fabrication of stacked vias, metal islands referred to as landing pads are introduced for the purpose of contact-connection between the vias that are arranged one above the other. The metal islands project laterally beyond the vias to a significant extent on account of the line shortening effect. The vias arranged in layers lying one above the other are laterally offset with respect to one another. The landing pad of the invention is configured as an interconnect running between the vias. On account of the line shortening effect, which is less critical for longer tracks, contact areas provided at the ends of the interconnect do not have to be chosen to be as large as the square contact areas of conventional metal islands and can therefore be accommodated to save more space on a circuit layout to be miniaturized. The shrink factor of such a semiconductor structure is increased.

Stacked via with specially designed landing pad for integrated semiconductor structures

A method for producing a semiconductor device having a first region with storage capacitors and a second region with at least one well surrounded by an insulation. The method creates both the storage capacitors and the insulation by forming trenches in the first region and at least one trench in the second region, and the trenches have a depth of at least 2 &mgr;m. The trenches in the first region are treated to provide first and second electrodes separated by a dielectric to form the capacitors and each trench in the second region provides an insulation which surrounds any wells in the second region.

Method for producing an insulation

The semiconductor structure has a layer structure formed from a metalization layer and a dielectric layer. The metalization layer is patterned and has contact areas. The dielectric layer is composed of a depositable material and covers the metalization layer. The contact areas are formed from many contiguous individual structures, which are so narrow that the depositable material does not form, over the individual structures, any areas which run parallel to the metalization layer. The grid of contiguous individual structures forms a contact area which causes dielectric layer elevations which are particularly low and therefore easy to planarize.

Patterning of content areas in multilayer metalization configurations of semiconductor components

A method for fabricating a microelectronic structure includes implanting nitrogen into a semiconductor substrate which is provided with trenches, at least in the region of a main area of the semiconductor substrate. The implantation is intended to be carried out in such a way that a nitrogen concentration at the main area is considerably greater than at the side walls of the trenches. As a result, during subsequent oxidation of the semiconductor substrate, a thinner oxide layer can be formed on the main area, in comparison with the side walls. The oxide layer has a homogeneous transition in the edge region between the main area and the side walls. Implanting nitrogen prior to the oxidation of the semiconductor substrate leads to a uniform oxide layer thickness on the main area.

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Radebeul, Germany

Albrecht Kieslich