Infineon Technologies Ag

Albino Pidutti

Damiano Gadler

Andrea Carletti

Ioannis Pachnis

Andrea Baschirotto

Robert Illing

Gebhart Dippold

Michael Lenz

Markus Ladurner

Paolo Del Croce

Daniel Mayer

Gerold Schrittesser

Alexander Mayer

Luca Petruzzi

Herbert Gietler

Alberto Zanardi

Stephane Fraisse

Francesca Romano

Yavuz Kilic

Bernhard Sorger

Roberto Di Lorenzo

Osvaldo Gasparri

A method for current measurement in a switching converter is described herein. In accordance with one embodiment, the method includes switching a first transistor on and off in accordance with a logic signal, wherein a load current passes through the first transistor while it is switched on. The method further includes providing—by a second transistor—a sense current that is indicative of the load current, wherein the second transistor is coupled to the first transistor so that the first and the second transistors are switched on and off simultaneously. Further, the method includes determining an end of a switch-on phase of the second transistor, and providing a current sense signal that represents the sense current between a first time instant, which corresponds to the determined end of the switch-on phase, and a second time instant, at which the logic signal signals a switch-off of the first transistor.

Intelligent semiconductor switch with integrated current measurement function

A gate driver circuit includes a pulse generator that receives an input signal and generates a pulse signal in response to a switch-on command included in the input signal. The pulse signal has a pulse with a pulse length that is dependent on a level of a pulse control signal. The circuit further includes a sampling circuit that samples an output voltage subsequent to the pulse and stores a respective sampled value, and a controller that receives the sampled value of the output voltage and a reference voltage and updates the level of the pulse control signal based on the sampled value and the reference voltage. A driver circuit generates the output voltage based on the pulse signal.

High speed driver for high frequency DCDC converter

An integrated circuit includes a transistor having a control electrode and a load current path to activate and to deactivate a load current path between a first terminal and a second terminal. A diode is in parallel with the load current path of the transistor. The integrated circuit includes a detector circuit to generate a control signal depending on a voltage between the first terminal and the second terminal. The integrated circuit includes a driver circuit having a main branch and a first feedforward branch. The main branch includes circuit components to generate a control voltage for the control electrode of the transistor in accordance with the control signal, and the feedforward branch comprises circuit components to generate a charging current or, alternatively, a discharging current as a reaction to a slope of the control signal, the current charging or discharging, respectively, the control electrode of the transistor.

Diode circuit

A rectifier device is described herein. In accordance with one embodiment, the rectifier device includes a semiconductor body doped with dopants of a first doping type and one or more well regions arranged in the semiconductor body and doped with dopants of a second doping type. The rectifier device further includes a controllable resistance circuit that is electrically connected between the semiconductor body and a first well region of one or more well regions and configured to provide a resistive current path between the semiconductor body and the first well region. The resistance of the current path is dependent on an instantaneous level of an alternating input voltage.

Rectifier device

A rectifier device includes a first transistor having a load current path and a diode connected in parallel to the load current path between an anode terminal and a cathode terminal. An alternating input voltage is operably applied between the anode terminal and the cathode terminal. A control circuit is coupled to a gate terminal of the first transistor and configured to switch the first transistor on for an on-time period, during which the diode is forward biased. A clamping circuit is coupled to the gate terminal of the first transistor and configured to at least partly switch on the first transistor while the diode is reverse biased and when the level of the alternating input voltage reaches a clamping voltage. The clamping circuit includes an additional circuit coupled between the cathode terminal and the gate terminal and configured to provide a voltage dependent on a load current.

Rectifier device with clamping circuit

A rectifier device is described herein. In accordance with one embodiment, the rectifier device includes a semiconductor body doped with dopants of a first doping type and one or more well regions arranged in the semiconductor body and doped with dopants of a second doping type. Thereby, the one or more well regions and the surrounding semiconductor body form a pn-junction. The rectifier device further includes an anode terminal and a cathode terminal connected by a load current path of a first MOS transistor and a diode, which is parallel to the load current path. An alternating input voltage is applied between the anode terminal and the cathode terminal during operation of the rectifier device. The rectifier device includes a control circuit that is configured to switch on the first MOS transistor for an on-time period, during which the diode is forward biased, wherein the first MOS transistor and the diode are integrated in the semiconductor body and the control circuit is at least partly arranged in the one or more well regions. Further, the rectifier device includes a switching circuit that is configured to electrically connect a first well region of the one or more well regions with the anode terminal, as long as the alternating input voltage is above a threshold value, and, to pull the voltage of first well region towards the alternating input voltage, as long as the alternating input voltage is at or below the threshold value.

A multi-channel device with a single diagnosis status pin may be configured to detect if one or more channels has a fault. The multi-channel device, which may operate within a system, can communicate which channel, of a plurality of channels, has the fault using only a single diagnosis status pin and no additional diagnosis control pins. The multi-channel device may output a fault signal on the diagnosis status pin and in response to an interrogation input signal on the same channel as a fault channel indicate to the system which channel is the fault channel.

Multi-channel fault detection with a single diagnosis output

A controller circuit is configured to drive a switching element to establish a channel that electrically couples a source to an inductive element of a buck converter and generate a minimum current sample. In response to current at the switching element exceeding a target peak current threshold of a set of control parameters for the buck converter, the controller circuit is configured to generate a peak current sample, calculate a mean current using the minimum current sample and the peak current sample, and modify the set of control parameters using the mean current. In response to the switching element satisfying an off time of the set of control parameters, the controller circuit is configured to drive the switching element to establish the channel that electrically couples the source to the inductive element during an on state for a subsequent switching period.

Power converter control using calculated average current

In one example, a method includes selectively activating, by control logic and based on a control signal, a switch; in response to determining that an electrical characteristic of a signal provided to the switch satisfies a threshold while the switch is deactivated, activating, by the control logic and regardless of the control signal, the switch until determining that a potential of the signal provided to the switch satisfies a threshold potential; and in response to determining that the potential of the signal provided to the switch satisfies the threshold potential, deactivating the switch.

Increase robustness of devices to overvoltage transients

A rectifier is described herein. According to one example, the rectifier includes a semiconductor substrate and further includes an anode terminal and a cathode terminal connected by a load current path of a first MOS transistor and a diode that is connected parallel to a load current path. An alternating input voltage is operably applied between the anode terminal and the cathode terminal. Further, the rectifier includes a control circuit that is configured to switch the first MOS transistor on for an on-time period, during which the diode is forward biased. The first MOS transistor, the diode, and the control circuit are integrated in the semiconductor substrate.

Rectifier device with safety threshold

In some examples, a device includes a set of switches configured to deliver current to an output node of the device, wherein the set of switches includes a first switch including a first control terminal and a second switch including a second control terminal, wherein a width-length ratio of the second switch is larger than a width-length ratio of the first switch, and wherein the first switch is electrically connected in parallel with the second switch. The device further includes control circuitry configured to deliver a first control signal to the first control terminal and deliver a second control signal to the second control terminal concurrently with delivering the first control signal to the first control terminal.

Control circuitry for controlling a set of switches

In some examples, a rectifier device includes a semiconductor substrate, an anode terminal and a cathode terminal connected by a load current path of a first MOS transistor and a diode connected parallel to the load current path. An alternating input voltage is operably applied between the anode terminal and the cathode terminal. Further, a control circuit is coupled to a gate electrode of the first MOS transistor and configured to switch on the first MOS transistor for an on-time period, during which the diode is forward biased. A gate driver circuit is included in the control circuit and includes a buffer capacitor and a cascade of two or more transistor stages connected between the buffer capacitor and the gate electrode of the first MOS transistor.

Gate driver circuit for a rectifier device including a cascade of transistor stages

A semiconductor device, overvoltage detection structure is described that includes a current path including a Zener diode connected in series with a fuse. The Zener diode is configured to conduct a current in response to an overvoltage condition at a semiconductor device and the fuse is configured to permanently break the current path of the overvoltage detection structure in response to the Zener diode conducting the current.

Device overvoltage detector

A rectifier device is described herein. In accordance with one exemplary embodiment, the rectifier device includes a semiconductor substrate doped with dopants of a first doping type and at least one well region arranged in the semiconductor substrate and doped with dopants of a second doping type. Accordingly, the at least one well region and the surrounding semiconductor substrate form a pn-junction. The rectifier device further includes an anode terminal and a cathode terminal connected by a load current path of a first MOS transistor and a diode connected parallel to the load current path. An alternating input voltage is operably applied between the anode terminal and the cathode terminal. The rectifier device further includes a control circuit and a biasing circuit. The control circuit is configured to switch on the first MOS transistor for an on-time period, during which the diode is forward biased. The first MOS transistor and the diode are integrated in the semiconductor substrate, and the control circuit is at least partly arranged in the at least one well region. The biasing circuit is configured to generate a biasing voltage that is applied to the at least one well region such that the pn-junction is reverse biased.

Growing community of inventors

Villach, Austria

Albino Pidutti