Arm Limited

Albin Pierrick Tonnerre

Frederic Claude Marie Piry

Luca Nassi

Peter Richard Greenhalgh

Ian Michael Caulfield

Geoffray Lacourba

Abhishek Raja

Cédric Denis Robert Airaud

Guillaume Bolbenes

Rémi Marius Teyssier

Paolo Monti

Yohan Fernand Fargeix

Houdhaifa Bouzguarrou

Alastair David Reid

Quentin Éric Nouvel

Thomas Christopher Grocutt

Milosch Meriac

Lee Evan Eisen

Yasuo Ishii

Stephan Diestelhorst

Matthew Lucien Evans

Andreas Lars Sandberg

Matthias Lothar Boettcher

Giacomo Gabrielli

Nikos Nikoleris

Håkan Lars-Göran Persson

Lucas Garcia

Vincenzo Consales

Timothy Hayes

Dominic Phillip Mulligan

François Donati

Damian Maiorano

Nathan Yong Seng Chong

Christophe Carbonne

Pasquale Ranone

Kias Magnus Bruce

Jeffrey Allen Kehl

Abdel Hadi Moustafa

Nicola Piano

Ilaria Bosco

Nathan Young Seng Chong

Apparatuses, systems, methods, computer-readable media, and computer code are disclosed. An apparatus comprises allocation circuitry configured to allocate store data comprising N portions in a store buffer. The store buffer comprises a data buffer configured to hold data entries, each data entry configured to hold one of the N portions of the store data; and an address buffer configured to hold address entries, wherein a given address entry is indicative of a memory address at which the store data is to be stored and is associated with N indications identifying one or more of the data entries that contain the store data. The allocation circuitry is responsive to a determination that M portions of the N portions of the store data each comprise duplicate data to set M indications of the N indications to identify a given data entry holding the duplicate data.

Allocation of store buffer entries

An apparatus is provided. Delegable memory accesses are offloaded to be performed by an external processing apparatus, whereas non-delegable memory accesses are performed locally. Nonetheless, an ordering requirement may still be enforced between them. The apparatus comprises tracking circuitry to maintain tracking information related to delegable memory accesses separately from tracking information related to non-delegable memory accesses. Order enforcement circuitry may enforce an ordering requirement between a non-delegable memory access and a delegable memory access based on a lookup of the tracking information.

Order enforcement for delegable memory accesses

Mode change detection circuitry detects a mode change when processing circuitry switches between first and second modes of processing in which a first set of architectural registers are designated as having different register lengths. Register mapping circuitry maps architectural registers to corresponding physical registers. For an operation specifying a given architectural register of the first set of architectural registers: in response to a determination that the operation is to be processed in the first mode of processing, the register mapping circuitry maps the given architectural register to a physical register of a first physical register file, and in response to a determination that the operation is to be processed in the second mode of processing, the register mapping circuitry maps the given architectural register to a physical register of a second physical register file separate from the first physical register file and having physical registers of different register length to physical registers of the first physical register file.

Register mapping to map architectural registers to corresponding physical registers based on a mode indicating a register length

There is provided an apparatus, method for data processing. The apparatus comprises post decode cracking circuitry responsive to receipt of decoded instructions from decode circuitry of a processing pipeline, to crack the decoded instructions into micro-operations to be processed by processing circuitry of the processing pipeline. The post decode cracking circuitry is responsive to receipt of a decoded instruction suitable for cracking into a plurality of micro-operations including at least one pair of micro-operations having a producer-consumer data dependency, to generate the plurality of micro-operations including a producer micro-operation and a consumer micro-operation, and to assign a transfer register to transfer data between the producer micro-operation and the consumer micro-operation.

Cracking instructions into a plurality of micro-operations

A data processing apparatus is provided which controls the use of data in respect of a further operation. The data processing apparatus identifies whether data is trusted or untrusted by identifying whether or not the data was determined by a speculatively executed resolve-pending operation. A permission control unit is also provided to control how the data can be used in respect of a further operation according to a security policy while the speculatively executed operation is still resolve-pending.

Controlling use of data determined by a resolve-pending speculative operation

A data processing apparatus is provided. Instruction send circuitry sends an instruction to an external processor to be executed by the external processor. Allocation circuitry allocates a specified one of several registers for a result of the instruction having been executed on the external processor and data receive circuitry receives the result of the instruction having been executed on the external processor and stores the result in the specified one of the several registers. In response to a condition being met: the specified one of the several registers is dereserved prior to the result being received by the data receive circuitry, and the result is discarded by the data receive circuitry when the result is received by the data receive circuitry.

Register freeing latency

An apparatus and method are provided for processing instructions. The apparatus has execution circuitry for executing instructions, where each instruction requires an associated operation to be performed using one or more source operand values in order to produce a result value. Issue circuitry is used to maintain a record of pending instructions awaiting execution by the execution circuitry, and prediction circuitry is used to produce a predicted source operand value for a chosen pending instruction. Optimisation circuitry is then arranged to detect an optimisation condition for the chosen pending instruction when the predicted source operand value is such that, having regard to the associated operation for the chosen pending instruction, the result value is known without performing the associated operation. In response to detection of the optimisation condition, an optimisation operation is implemented instead of causing the execution circuitry to perform the associated operation in order to execute the chosen pending instruction. This can lead to significant performance and/or power consumption improvements.

Apparatus and method for predicting source operand values and optimized processing of instructions

In response to a single-copy-atomic load/store instruction for requesting an atomic transfer of a target block of data between the memory system and the registers, where the target block has a given size greater than a maximum data size supported for a single load/store micro-operation by a load/store data path, instruction decoding circuitry maps the single-copy-atomic load/store instruction to two or more mapped load/store micro-operations each for requesting transfer of a respective portion of the target block of data. In response to the mapped load/store micro-operations, load/store circuitry triggers issuing of a shared memory access request to the memory system to request the atomic transfer of the target block of data of said given size to or from the memory system, and triggers separate transfers of respective portions of the target block of data over the load/store data path.

Handling of single-copy-atomic load/store instruction with a memory access request shared by micro-operations

Apparatuses and methods relating to controlling cache evictions are disclosed. Processing circuitry which execute instructions out-of-order is provided with a private cache into which blocks of data are copied from a shared storage location to which the processing circuitry shares access. The processing circuitry also has a read-after-read buffer, into which an entry is allocated when out-of-order execution of a load instruction occurs comprising an address accessed by the load instruction. The address remains as a valid entry in the read-after-read buffer until the load instruction is committed. Eviction of an eviction candidate block of data from the private cache to the shared storage location is controlled in dependence on whether the eviction candidate block of data has a corresponding valid entry in the read-after-read buffer.

Cache eviction control for a private cache in an out-of-order data processing apparatus

Circuitry comprises a translation lookaside buffer to store memory address translations, each memory address translation being between an input memory address range defining a contiguous range of one or more input memory addresses in an input memory address space and a translated output memory address range defining a contiguous range of one or more output memory addresses in an output memory address space; in which the translation lookaside buffer is configured selectively to store the memory address translations as a cluster of memory address translations, a cluster defining memory address translations in respect of a contiguous set of input memory address ranges by encoding one or more memory address offsets relative to a respective base memory address; memory management circuitry to retrieve data representing memory address translations from a memory, for storage by the translation lookaside buffer, when a required memory address translation is not stored by the translation lookaside buffer; detector circuitry to detect an action consistent with access, by the translation lookaside buffer, to a given cluster of memory address translations; and prefetch circuitry, responsive to a detection of the action consistent with access to a cluster of memory address translations, to prefetch data from the memory representing one or more further memory address translations of a further set of input memory address ranges adjacent to the contiguous set of input memory address ranges for which the given cluster defines memory address translations.

Memory address translation

Apparatuses and methods are disclosed for performing data processing operations in main processing circuitry and delegating certain tasks to auxiliary processing circuitry. User-specified instructions executed by the main processing circuitry comprise a task dispatch specification specifying an indication of the auxiliary processing circuitry and multiple data words defining a delegated task comprising at least one virtual address indicator. In response to the task dispatch specification the main processing circuitry performs virtual-to-physical address translation with respect to the at least one virtual address indicator to derive at least one physical address indicator, and issues a task dispatch memory write transaction to the auxiliary processing circuitry comprises the indication of the auxiliary processing circuitry and the multiple data words, wherein the at least one virtual address indicator in the multiple data words is substituted by the at least one physical address indicator.

Task dispatch

An apparatus comprises processing circuitryto perform data processing in response to instructions, the processing circuitry supporting speculative processing of read operations for reading data from a memory system; and control circuitryto identify whether a sequence of instructions to be processed by the processing circuitry includes a speculative side-channel hint instruction indicative of whether there is a risk of information leakage if at least one subsequent read operation is processed speculatively, and to determine whether to trigger a speculative side-channel mitigation measure depending on whether the instructions include the speculative side-channel hint instruction. This can help to reduce the performance impact of measures taken to protect against speculative side-channel attacks.

Speculative side-channel hint instruction

An apparatus and method of operating a data processing apparatus are disclosed. The apparatus comprises data processing circuitry to perform data processing operations in response to a sequence of instructions, wherein the data processing circuitry is capable of performing speculative execution of at least some of the sequence of instructions. A cache structure comprising entries stores temporary copies of data items which are subjected to the data processing operations and speculative execution tracking circuitry monitors correctness of the speculative execution and responsive to indication of incorrect speculative execution to cause entries in the cache structure allocated by the incorrect speculative execution to be evicted from the cache structure.

Tracking speculative data caching

Examples of the present disclosure relate to an apparatus comprising execution circuitry to execute instructions defining data processing operations on data items. The apparatus comprises cache storage to store temporary copies of the data items. The apparatus comprises prefetching circuitry to a) predict that a data item will be subject to the data processing operations by the execution circuitry by determining that the data item is consistent with an extrapolation of previous data item retrieval by the execution circuitry, and identifying that at least one control flow element of the instructions indicates that the data item will be subject to the data processing operations by the execution circuitry; and b) prefetch the data item into the cache storage.

Apparatus and method for prefetching data items

An apparatus and method are provided for controlling allocation of instructions into an instruction cache storage. The apparatus comprises processing circuitry to execute instructions, fetch circuitry to fetch instructions from memory for execution by the processing circuitry, and an instruction cache storage to store instructions fetched from the memory by the fetch circuitry. Cache control circuitry is responsive to the fetch circuitry fetching a target instruction from a memory address determined as a target address of an instruction flow changing instruction, at least when the memory address is within a specific address range, to prevent allocation of the fetched target instruction into the instruction cache storage unless the fetched target instruction is at least one specific type of instruction. It has been found that such an approach can inhibit the performance of speculation-based caching timing side-channel attacks.

Growing community of inventors

Nice, France

Albin Pierrick Tonnerre