Stmicroelectronics S.r.l.

Sgs-thomson Microelectronics S.r.l.

Sgs-microelectronics S.r.l.

Alberto Taddeo

Angelo Moroni

Flavio Scarra

Flavio Scarra'

A sense amplifier for reading a memory cell is provided. The sense amplifier includes a first input branch for applying a biasing voltage to the memory cell through regulation means and for receiving a first input current indicative of a state of the memory cell, the regulation means including a first controlled element having a voltage-controlled conductivity and a control element for applying a first control voltage corresponding to the first input current to the first controlled element, and sensing means for determining the state of the memory cell according to a comparison between the first input current and a reference value; the sensing means includes a second input branch including a second controlled element (M), shifting means () for applying a second control voltage equal to the first control voltage shifted by a predetermined offset to the second controlled element, a second input current corresponding to the second control voltage flowing through the second input branch, and comparison means for comparing the second input current with the reference value.

Sense amplifier for low-voltage applications

A current sense amplifier, in particular for low voltage applications, of the type incorporated in a memory electronic device and including a differential amplifier having inputs respectively associated with a matrix circuit leg, connected to a cell to be sensed, and a reference circuit leg, connected a reference cell. At least the matrix circuit leg has a first MOS transistor to which an inverter is connected in a cascode configuration and a first input of the differential amplifier corresponding to the matrix circuit leg is coupled to a conduction terminal of the first MOS transistor and to the bitline of the memory matrix by a second MOS transistor.

Current sense amplifier for low voltage applications with direct sensing on the bitline of a memory matrix

A circuit for generation of a reset signal in an electronic device, of the type comprising a microprocessor interlocked with a circuit generating a clock signal and memories of both the volatile type and the non-volatile type, is capable of detecting a stop in the oscillation of said clock signal and generating a logic signal coupled with the reset input of the microprocessor.

Circuit for detecting a fault state in a clock signal for microprocessor

An electronic device including a microprocessor, a circuit generating a clock signal, and memories of both the volatile type and the non-volatile type, incorporates a circuit for generation of a reset signal capable of detecting a stop in the oscillation of said clock signal and generating a logic signal coupled with the reset input of the microprocessor. The circuit monitors the clock signal applied to the device and, if an irregularity is detected, generate a reset signal holding the microprocessor in a safe state. The reset signal is held until the circuit generating the clock signal resumes normal operation.

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Arenzano, Italy

Alberto Taddeo