Palo Alto Research Center Inc.

Leland Stanford Junior University

Xerox Corporation

Alberto Salleo

William S Wong

Michael L Chabinyc

Raj B Apte

Jeng Ping Lu

Stephen David White

Robert Anthony Street

Steven E Ready

Peter Peumans

David G Duff

Christian G Van De Walle

Saahil Mehra

Mark Greyson Christoforo

Ana Claudia Arias

Jennifer Anne Dionne

James Randy Groves

Bruce M Clemens

Garrett J Hayes

Michael L Chebinyc

Bingrui Joel Li

Di Meng Wu

Waqas Mustafeez

A biaxially textured crystalline layer formed on a substrate using ion beam assisted deposition (IBAD) is provided. The biaxially textured crystalline layer includes an oriented CaFcrystalline layer having crystalline grains oriented in both in-plane and out-of-plane directions, where the out-of-plane orientation is a (111) out-of-plane orientation. The oriented CaFcrystalline layer is disposed for growth of a subsequent epitaxial layer and the CaFcrystalline layer is an IBAD CaFlayer. The biaxially textured CaFlayer can be used in a photovoltaic cell, an electronic or optoelectronic device, an integrated circuit, an optical sensor, or a magnetic device.

Depositing calcium fluoride template layers for solar cells

In one embodiment, a method is provided for fabrication of a semitransparent conductive mesh. A first solution having conductive nanowires suspended therein and a second solution having nanoparticles suspended therein are sprayed toward a substrate, the spraying forming a mist. The mist is processed, while on the substrate, to provide a semitransparent conductive material in the form of a mesh having the conductive nanowires and nanoparticles. The nanoparticles are configured and arranged to direct light passing through the mesh. Connections between the nanowires provide conductivity through the mesh.

Deposition and post-processing techniques for transparent conductive films

An up-converting electrode and a solar cell that combines the up-converting electrode are disclosed. The up-converting electrode comprises a material that up-converts light from longer wavelengths to shorter wavelengths and an electrically conductive material. The electrically conductive material increases the efficiency of the up-converting material such that more light is up-converted. The up-converting electrode can also serve as an electrical contact for the solar cell.

Composition and method for upconversion of light and devices incorporating same

A 1D nanobeam photonic crystal cavity is provided that includes a substrate, where the substrate includes a dielectric medium, and a series of cutout features in the substrate, where each cutout feature includes a first curved surface and a second curved surface, where the first curved surface and the second curved surface form a meniscus shape, where the series of cutout features include an array of sizes of the meniscus shape cutouts, where edges of the meniscus shape and the array of sizes are disposed to form a pair of opposing parabolic dips proximal to a central region of the series of cutout features.

Confocal and concave 1D photonic crystal resonant cavities with ultra-low mode volume

Composite films formed from blends of semiconducting and insulating materials that phase separate on patterned substrates are provided. Phase separation provides isolated and encapsulated areas of semiconductor on the substrate. Processes for preparing and using such composite films are also provided, along with devices including such composite films.

Phase-separated composite films and methods of preparing the same

Black matrix (BM) material is deposited on glass and patterned to form walls that define an array of wells. Various surface treatments and masking schemes are utilized to achieve surface energy control of the BM glass. The surface treatments include one or more of chemically treating the BM walls by depositing hydrophobic self-assembled monolayers on the uppermost wall surfaces, and plasma treatments to control the surface energy of the various BM glass surfaces. Masking processes include backside exposure and development of photoresist, and maskless, self-aligned photo-patterning of the monolayers. Color filter ink is then injected into each well from an ink jet print head. The high surface energy of the lower and side wall surfaces facilitates wetting of the ink, and the low surface energy of the monolayers prevents intermixing of ink between adjacent wells. The ink then dries to form a color filter in each well.

Surface energy control methods for color filter printing

An improved fuel cell is described. The invention addresses the problem of mechanical failure in thin electrolytes. One embodiment varies the thickness of the electrolyte and positions at least either the anode or cathode in the recessed region to provide a short travel distance for ions traveling from the anode to the cathode or from the cathode to the anode. A second embodiment uses a uniquely shaped manifold cover to allow close positioning of the anode to the cathode. Using the described structures results in a substantial improvement in fuel cell reliability and performance.

Micro-machined fuel cells

An improved transistor array for a display or sensor device is described. The display or sensor device includes a plurality of pixels. Each pixel includes a width and a length. Each pixel is addressed by a transistor. The transistor addressing each pixel has a channel with a channel width. Each channel width is greater than the width or length of the pixel being addressed. By fabricating transistors with extremely long channel widths, lower mobility semiconductor materials can easily be used to fabricate the display device.

Thin-film transistor array with ring geometry

An electronic device and a method of fabricating the electronic device includes forming a first electrical contact, a dielectric layer and a second electrical contact wherein the dielectric layer is located between the first and the second electrical contacts, forming an electrically insulating layer over the dielectric layer and the first electrical contact, exposing the first and second electrical contact, the dielectric layer and a first portion of the electrically insulating layer to radiation from the side of the first electrical contact, removing a second portion of the electrically insulating layer that was not irradiated by the radiation, providing a semiconductor material over a portion of the dielectric layer, and forming at least a third electrical contact over at least a portion of the electrically insulting layer and the semiconductor material.

Electronic device and methods for fabricating an electronic device

A method and system for masking a surface to be etched is described. The method includes the operation of heating a phase-change masking material and using a droplet source to eject droplets of a masking material for deposit on a thin-film or other substrate surface to be etched. The temperature of the thin-film or substrate surface is controlled such that the droplets rapidly freeze after upon contact with the thin-film or substrate surface. The thin-film or substrate is then treated to alter the surface characteristics, typically by depositing a self assembled monolayer on the surface. After deposition, the masking material is removed. A material of interest is then deposited over the substrate such that the material adheres only to regions not originally covered by the mask such that the mask acts as a negative resist. Using such techniques, feature sizes of devices smaller than the smallest droplet printed may be fabricated.

Method for fabricating fine features by jet-printing and surface treatment

Two different processing techniques are utilized to respectively form high resolution features and low resolution features in a critical layer of an electronic device, and in particular a large area electronic device. High resolution features are formed by soft lithography, and low resolution features are formed by jet-printing or using a jet-printed etch mask. Jet-printing is also used to stitch misaligned structures. Alignment marks are generated with the features to coordinate the various processing steps and to automatically control the stitching process. Thin-film transistors are formed by generating gate structures using a first jet-printed etch mask, forming source/drain electrodes using soft lithography, forming interconnect structures using a second jet-printed etch mask, and then depositing semiconductor material over the source/drain electrodes. Redundant structures are formed to further improve tolerance to misalignment, with non-optimally positioned structures removed (etched) during formation of the low resolution interconnect structures.

Large area electronic device with high and low resolution patterned film features

A method of patterning soluble materials on a substrate is described. In the method, a stamp is applied to a liquid carrier solution. The raised areas of the stamp removes mainly a liquid carrier leaving behind a precipitate while the non-raised areas of the stamp lifts both the liquid carrier and the precipitate from the substrate. The result is a precipitate pattern residue that matches the raised area of the stamp. One use of the method is for patterning large areas of polymers used in large area electronics such as displays and sensors.

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San Francisco, CA, United States of America

Alberto Salleo