Stmicroelectronics S.r.l.

Sgs-thomson Microelectronics S.r.l.

Stmicroelectronics Gmbh

Sgs Microelettronica Spa

Alberto Salina

Gianluca Ventura

Donatella Brambilla

Ezio Galbiati

Domenico Rossi

Claudio Diazzi

Michele Berto Boscolo

Maurizio Nessi

Marco Viti

Giorgio Pedrazzini

Francesco Chrappan Soldavini

Lorenzo Papillo

Andrea Merello

Roberto Peritore

Sandro Cerato

Francesco Vavala

Francesco Chrappan

Alessandra Schenone

Fabio Ramaioli

Luca Anostini

A multi-chip system in which at least one of the chips includes a performance parameter encoded thereon. After system assembly, the performance parameter can be obtained by a companion chip and used to automatically or semi-automatically fine tune the companion chip to the specific parameters of the at least one chip.

Performance tuning using encoded performance parameter information

A disk drive system is described which includes a disk having a magnetic surface and a motor for rotating the disk, a magnetic head being movable relative to said magnetic surface. The motor generates a back electromotive force voltage having different phases and the system comprising a plurality of switches for switching the back electromotive force voltage, a control circuit to control the plurality of switches to supply the back electromotive force voltage to direct the head to a parking position. The system also comprises a comparator adapted to compare a single phase of the back electromotive force voltage with the sum of the other phases of the back electromotive force voltage. The comparator generates an output signal representative of the comparation and the system comprises a logic block controlled by the output signal of the comparator. The logic block is adapted to determine time periods and a control sequence of the switches which is associated to the time periods. The control sequence is supplied to the control circuit so that the last generates control signals to control the plurality of switches.

Disk drive system and method for operating same

The present invention relates to the positioning of the read/write transducer heads of an hard disk (HD) in a designated landing zone when requested or when the electrical power is removed from the drive. In particularly it relates to the detection of the back electromotive force (BEMF) of the motor involved in the positioning of the read/write transducer heads. According to an embodiment of the present invention a BEMF detection circuit for a voice-coil motor operative to continually generate a signal proportionally to the velocity of said voice-coil motor comprises a algebraic summing node producing at its output the BEMF of the voice-coil motor and receiving: a first voltage proportional to the voltage across the voice-coil motor; a second voltage representing the product of a first multiplier factor and a voltage proportional to the current in the coil; a third voltage representing the product of a prefixed bias voltage Vref and a second multiplier factor; said third voltage is calibrated by a single calibration circuitry operative to calibrate said second multiplier factor in response to a calibration control signal, in order to cancel said second voltage.

Calibration technique of a BEMF detector

In a current mode pulse width modulation (PWM) integrated drive system having an external load, a switched-capacitor amplifier and a sample & hold stage connected in cascade form a current sensing amplifier for a control loop. The current sensing amplifier overcomes resistive mismatchings, thus permitting a scaling down of the supply voltage with high precision for the integrated drive system.

Integrated current mode PWM drive system supply voltage scaleable while retaining a high precision

The operation of externally connected output power transistors of a class AB amplifier is controlled without employing any external sensing resistance of the output current by driving an externally connected power transistor through a level shifting buffer and employing a limiting network composed of an integrated transistor driven by the output of a signal amplifying stage and a resistance connected in series with its drain. The buffer stage shifts the level of the driving signal of the external power transistor by a value equal to the threshold voltage of the integrated transistor of the limiting network thus ensuring the turn-off of the external power transistor under quiescent conditions.

Integrated unit gain output stage

Monitoring of current flowing through an inductive load driven through a bridge power stage in a PWM mode, comprises sampling the signal output by a sensing amplifier with a Sample & Hold circuit including a sampling switch and a storing capacitor. The average value of the current in the load is monitored by sampling at a half way point of an active driving phase and at a half way point of a current recirculation phase by closing the switch with a synchronizing pulse that coincides with the half way points of these phases of operation. The monitoring uses a pair of complementary periodic reference signals and uses a sensing amplifier to amplify the signal existing on a current sensing resistor functionally connected in series with the load. This produces an amplified signal representative of the current in the load to be fed to an input of an error amplifier driving a power amplifier of the bridge stage. The synchronizing pulse is generated in coincidence with the peak and with the virtual zero crossing of the two reference periodic signals, out of phase from one another by 180 degrees. A two-input logic AND gate, combining the synchronizing pulse and a masking signal of a preestablished duration generated at every switching of the bridge stage may also be employed.

Monitoring of current in an inductive load, PWM driven through a bridge

A mixed mode PWM/Linear driving system for at least one inductive-resistive (L-R) actuator as a function of operating conditions thereof includes a first full bridge power stage including four power switching devices arranged in pairs for being driven in phase opposition. The system also includes a pulse width modulation (PWM) converter for producing a PWM signal directly driving the first full bridge power stage during a PWM mode operating phase. A second full bridge power stage also comprises four power switching devices of different electrical characteristics from the power switching devices of the first full bridge power stage. The system further includes a pair of amplifiers connected to respective pairs of power switching devices of the second full bridge power stage for driving same in phase opposition during a linear mode operating phase. A switch is provided for switching between the PWM mode operating phase and the linear mode operating phase.

Mixed PWM/linear mode driving system employing two distinct output power

The sensing of the rotor position for synchronizing the drive of a multi-phase brushless motor when driven in a 'multi-polar' mode is carried out by interrupting the driving current in at least one of the windings of the motor coupled with a zero-cross sensing circuit of the BEMF signal. This done by using a first logic signal, enabling a logic gate for asserting a zero-cross event detected by the circuit by a third logic signal, and simultaneously resetting the first signal and the third signal after a certain period of time from the instant of interruption.

Detection of instantaneous position of the rotor of a brushless DC motor

A device presenting pairs of split contact pad portions, each pair of pads having multiple bonding wire, and metal connecting strips associated therewith. The end portion of the metal connecting strips being split into parallel strip segments, each connected to a respective contact pad, so as to form a plurality of parallel current paths between a node and an external contact pin connected to the node. When current is supplied along the connecting strip a voltage drop along each segment connected to a sound bonding wire is produced, but not along the segments connected to broken or non-bonded wires. By determining the existence of a voltage difference between the contact pad portions, it is possible to detect the interruption of one or more of the bonding wires.

Electronic device for testing bonding wire integrity

A CMOS logic circuit for sampling data coming from TTL logic circuits under frequency control by a system's clock intrinsically faster than prior art similar circuits is obtained by combining a TTL/CMOS compatibility interface inverting stage with a first stage of the sampling circuit (master or latch stage). The circuit of the invention permits elimination of two inverters and therefore reduction of data transfer delay.

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Limbiate, Italy

Alberto Salina