Sharp Kabushiki Kaisha Corporation

Yazaki Corporation

Tohoku University

Alberto Oscar Adan

Kenichi Higashi

Hisao Ichijo

Mitsuhiro Kikuta

Tadahiro Ohmi

Seiji Kaneko

Akinobu Teramoto

Takanori Watanabe

Jun Kudo

Hiroo Yabe

Hidenori Morimoto

Toshinori Ohmi

Kazushi Naruse

Norihiro Tokuyama

Shinji Kamiya

Koji Fujimoto

Motoharu Arimura

Kenichi Niimi

Masayoshi Horita

Atsushi Kagisawa

A P type semiconductor substrate includes a P type body region, an N type drift region formed away from the P type body region in a direction parallel to a substrate surface, an N type drain region formed in a region separated by a field oxide film in the N type drift region so as to have a concentration higher than the N type drift region, an N type source region formed in the P type body region so as to have a concentration higher than the N type drift region. A P type buried diffusion region having a concentration higher than the N type drift region is formed of a plurality of parts each of which is connected to a part of the bottom surface of the P type body region and extends parallel to the substrate surface and its tip end reaches the inside of the drift region.

Semiconductor device and method for producing the same

In a power IC device, a surface layer channel CMOS transistor and a trench power MOS transistor are formed on the same chip. In one embodiment, a source region of the trench power MOS transistor is arranged at the same level as a gate electrode of the surface layer channel CMOS transistor. Thus, the power IC device and a method for manufacturing the power IC device are provided for reducing manufacturing cost in the case of forming the trench power MOS transistor and the surface layer channel CMOS transistor on the same chip.

Power IC device and method for manufacturing same

Provided are a semiconductor device which can be manufactured at low cost and has a low on-resistance and a high withstand voltage, and its manufacturing method. The semiconductor device comprises an N-type well area formed on a P-type semiconductor substrate, a P-type body area formed within the well area, an N-type source area formed within the body area, an N-type drain area formed at a distance from the body area within the well area, a gate insulating film formed so as to overlay a part of the body area, a gate electrode formed on the gate insulating film and a P-type buried diffusion area which makes contact with the bottom of the body area and extends to an area beneath the drain area in a direction parallel to the surface of the semiconductor substrate within the well area.

Semiconductor device and its manufacturing method

In one embodiment of the present invention, a power IC device is disclosed containing a power MOS transistor with a low ON resistance and a surface channel MOS transistor with a high operation speed. There is also provided a method of manufacturing such a device. A chip has a surface of which the planar direction is not less than &#x2212;8&#xb0; and not more than +8&#xb0; off a silicon crystal face. The p-channel trench power MOS transistor includes a trench formed vertically from the surface of the chip, a gate region in the trench, an inversion channel region on a side wall of the trench, a source region in a surface layer of the chip, and a drain region in a back surface layer of the chip. The surface channel MOS transistor has an inversion channel region fabricated so that an inversion channel current flows in a direction not less than &#x2212;8&#xb0; and not more than +8&#xb0; off the silicon crystal direction.

Power IC device and method of manufacturing same

In an embodiment of the present invention, a Trench MOSFET includes a trench region provided on a semiconductor substrate. The semiconductor substrate includes a P-type semiconductor substrate, a P-type semiconductor epitaxial layer, an N-type semiconductor body region, and a P-type semiconductor source diffusion. The substrate, the epitaxial layer, the body region, and the source diffusion are adjacently formed in this order. A P-type semiconductor channel region formed of a SiGe layer is provided on a bottom surface and a side wall of the trench region. This facilitates carrier movement in the channel region, reducing ON resistance of the Trench MOSFET. Thus, a Trench MOSFET allowing reduction in the ON resistance without reducing a breakdown voltage is realized.

Trench type MOSFET and method of fabricating the same

A frequency conversion circuit of the present invention includes: (i) a first mixer for mixing the radio frequency signal having a frequency fwith a first oscillation signal having a frequency fso that the radio frequency signal is downconverted into an intermediate frequency signal; and (ii) a second mixer for mixing the intermediate frequency signal sent from the first mixer with two local oscillation signals so that the intermediate frequency signal is downconverted into two base-band signals having different phases. The second local oscillation signals have phases of 0&#xb0; and 270&#xb0;, respectively. These frequencies satisfies:f(f=f/m, (m&#x3e;1)k=m/(m&#x2212;1).This arrangement ensures (i) a small frequency conversion circuit that can be mounted on an integrated circuit, (ii) a radio frequency receiver including the frequency conversion circuit, and (iii) a radio frequency transceiver including the radio frequency receiver.

Frequency conversion circuit, radio frequency wave receiver, and radio frequency transceiver

A field effect transistor of the present invention includes, on a semiconductor substrate, (i) a fin section formed in a fin shape protruding from the substrate, (ii) a gate dielectric for covering a channel region section of the fin section, (iii) a gate electrode that is insulated from the channel region section by the gate dielectric and is formed on the channel region section and (iv) an insulating layer for covering a surface of the semiconductor substrate. The fin section is formed so as to extend from the semiconductor substrate through the insulating layer and protrudes outward from a surface of the insulating layer. In this way, the channel region of the fin section is physically in contact with the substrate.

Field effect transistor and fabrication method thereof

The oscillator includes: a first oscillator circuit in which first and second transistors cross-connected to each other are connected to a resonant circuit; and a second oscillator circuit in which third and fourth transistors cross-connected to each other are connected to a resonant circuit, wherein a coupling capacitor and coupling resistor are serially provided between a collector terminal of the first transistor and a base terminal of the fourth transistor, and a coupling capacitor and coupling resistor are serially provided between a collector terminal of the second transistor and a base terminal of the third transistor, and a coupling capacitor and coupling resistor are serially provided between a collector terminal of the third transistor and a base terminal of the first transistor, and a coupling capacitor and coupling resistor are serially provided between a collector terminal of the fourth transistor and a base terminal of the second transistor. On this account, it is possible to suppress noises and reduce power consumption.

Serially RC coupled quadrature oscillator

A variable gain amplifier circuitincludes an amplifier A, an amplifier A, an inductor L, and an inductor L. The amplifier Ahas a predetermined gain and is connected at a terminal to a circuit output section. The amplifier Ahas a different gain from the amplifier Aand is connected at a terminal to the circuit output section. The inductor Lis connected at an end to a circuit input section and at the other end to the input terminal of the amplifier A. The inductor Lis connected at an end to ground and at the other end to the input terminal of the amplifier A. The inductors Land Lform a transformer T. The configuration restricts input impedance variations which are dependent on the signal path taken by an input signal Vin. The input impedance and the signal source impedance remain matched. Impedance matching is preformed with the signal source with variable gain.

Variable gain amplifier circuit

In order to reduce capacitance of a feedback section of an operational amplifier provided in a semiconductor integrated device, an active filter includes an operational amplifier in which a plurality of capacitive elements are connected between (i) an output terminal and (ii) an inverting input terminal or an input terminal. This arrangement does not require any special technique and amendment of an ordinary integrated circuit process. Further, this arrangement ensures small capacitance in the feedback section of the operational amplifier, while preventing deterioration in S/N ratio, and increases in switching noise and power consumption.

Active filter

A phase locked loop circuit includes a phase comparator and a charge-pump circuit. The phase comparator and the charge-pump circuit are configured to satisfy the relationship of K&#x3e;Kin an I&#x2212;&#x394;&#x3c6; characteristic, where Kindicates a slope Kin the case where |&#x394;&#x3c6;|&#x3e;&#x394;&#x3c6;, Kindicates a slope Kin the case where |&#x394;&#x3c6;|&#x2266;&#x394;&#x3c6;, Kbeing defined by K=dI/d&#x394;&#x3c6;, and &#x394;&#x3c6;being a constant indicating a predetermined phase error.

Phase locked loop circuit

A lamination of metal wire layers forms an electromagnetic isolation structure. The metal wire layers are connected with each other by vias, so that a metal fence having a laminated structure is formed. The metal fence is provided so as to surround an element (e.g. a spiral inductor) that generates an electromagnetic field in an integrated circuit. The metal wire satisfies d&#x2266;&#x3bb;/8, WF&#x2267;5&#x3b4;, and L&#x2266;&#x3bb;/20, where &#x3b4; is a skin depth of an electromagnetic wave, c is a velocity of light, f is an operating frequency of the integrated circuit, d is a lateral-direction size of a metal-fence region, WF is a surrounding-line width of the metal fence, L is an interval between the vias, and &#x3bb;=c/f is a wavelength of a signal. With this arrangement, it is possible to decrease electromagnetic coupling noises and coupling noises caused via the substrate.

Integrated circuit

A the present invention provides an electrostatic discharge protection element to be used in a semiconductor integrated circuit providing MOSFET, comprising a thyristor and a trigger diode for triggering the thyristor into an ON-state, wherein the trigger diode provides an n-type cathode high concentration impurity region, a p-type anode high concentration impurity region and a gate formed between the two high concentration impurity regions, the gate being composed of the same material as that of a gate of MOSFET forming the semiconductor integrated circuit, and the thyristor provided with a p-type high concentration impurity region that forms a cathode and an n-type high concentration impurity region that forms an anode, and the p-type high concentration impurity region provides in a p well and connected to a resistor and/or the n-type high concentration impurity region provided in an n well and connected to a resistor.

Electrostatic discharge protection element

In a multi-terminal MOS varactor, a floating electrode of a MOS capacitor (Cf) is connected to one of two terminals of each of a plurality of capacitors (C -Cn) - through - . To the other terminals (Vg -Vgn) - through - of the respective capacitors (C -Cn) - through - , control voltages Vg Vgn are applied, and a terminal (Vn) of the MOS capacitor (Cf) , the terminal being on the side of a well, receives a control voltage. In the multi-terminal MOS varactor with the arrangement above, it is possible to progressively change the valid electrostatic capacity C of the other terminal (Vgj) - of an arbitrary capacitor (Cj) - , by changing the control voltage. Since electrostatic capacity can be progressively changed in this MOS varactor, adopting this MOS varactor to an oscillator enables to control a frequency and sensitivity of the oscillator.

Multi-terminal MOS varactor

A semiconductor device including an insulating film, a plurality of word lines parallel to one another, a gate insulating film and a first conductivity type semiconductor layer that are formed in this order, wherein the surface of said insulating film is rendered flat with respect to the surface of the word lines, and the first conductivity type semiconductor layer includes bit lines comprising a plurality of second conductivity type high concentration impurity diffusion layers crossing the word lines and parallel to one another.

Growing community of inventors

Ikoma, Japan

Alberto Oscar Adan