Agere Systems Inc.

Massana Research Limited

Agere Systems (Ireland) Research Limited

Alberto Molina Navarro

Philip Curran

Carl Murray

Ciaran McElroy

Stephen Bates

Carl Damien Murray

In a 1000 BASE-T transceiver, a timing error detector (TED,) receives its inputs directly from the output of an ADC () and from a decision device (). Timing recovery is acquired in three stages: a non-decision directed (NDD) stage during which only the output of an ADC () are used for acquisition; a stage for acquiring the remote scrambler and predicting symbols; and a decision-directed (DD) stage during which locally predicted symbols are also used for acquisition. Because the timing error detector (TED,) does not take inputs from the FFE () there is no information about cable length, and so an input of gain from an AGC is used to indicate cable length.

Timing recovery in data communication circuits

Channel equalization in a 1000BASE-T receiver is performed by a fixed mode analog filtersuitable for the longest possible cable length, by a FFE (), and by a digital filter. The digital filter () has two sets of taps. One set is optimal for shorter cable lengths and so cancels adaptation for long cable lengths and assists operation of the analog filter. A decision block () selects an appropriate set of taps.

Channel equalization in data receivers

A FIR filter in a Gigabit transceiver in which data words are represented in three bits: SIGN representing word sign, SHIFT representing requirement for a shift operation, and ZERO indicating whether the word is zero. An AND gate ANDs an input coefficient and the ZERO bit, an XOR gate XORs the SIGN bit and the output of the AND gate, and a multiplier left-shifts the coefficient using the SHIFT bit and the output of the XOR gate. The circuit has a very low gate count.

Processing of quinary data

A Gigabit transceiver () has a receiver () and a transmitter (). There is an ADC () in the receiver () for each channel (A, B, C, D). The ADCs () oversample at a factor of 2. However the remainder of the digital circuitry and transmitter DACs () operate off half of the oversampling rate. In the receiver () fractionally spaced equalisers (FSES,) ensure that the optimum sampling phase is selected digitally. The invention avoids the need for a PLL in the receiver for each channel and associated interference and retiming problems.

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Madrid, Spain

Alberto Molina Navarro