Analog Devices,inc.

Analog Devices International Unlimited Company

Analog Devices Global Unlimited Company

Alberto Marinas

Eoin Edward English

Erik Barnes

Santiago Iriarte

Eduardo M Martinez

Colm Donovan

Siwen Liang

Junhua Shen

Jesus Javier Lopez

Marlon Consuelo Maramba

Gary Casey

Erik D Barnes

Daniel Peter Canniff

Christian Jimenez

Sivanendra Selvanayagam

Roberto Munoz

Jose Ibanez Climent

Pedro Lopez Canova

Provided herein are delay locked loops (DLLs) with calibration for external delay. In certain embodiments, a timing alignment system includes a DLL including a detector that generates a delay control signal based on comparing a reference clock signal to a feedback clock signal, and a controllable delay line configured to generate the feedback clock signal by delaying the reference clock signal based on the delay control signal. The timing alignment system further includes a delay compensation circuit that provides an adjustment to the controllable delay line to compensate for a delay of the feedback clock signal in reaching the detector.

Delay locked loops with calibration for external delay

A time-of-flight (ToF) transmitter with self-stabilized optical output phase with minimal overhead is described, where the transmitter may either function as a slave in that the laser pulse phase and width can be controlled by the master ToF receiver, or it can function as a master where the laser control pulse is generated on the same chip or a companion chip. When the ToF transmitter functions as a slave and receives the laser pulse control signal, the techniques of this disclosure can transform the receive path and the pre-driver circuit into part of a delay locked loop (DLL).

Time of flight transmitter with self-stabilized optical output phase

The present disclosure provides a feedback control system and method for a bidirectional VCM. The system employs an analog core that is common to both the PWM and linear modes of operation. The analog core includes a feedback mechanism that determines the error in the current flowing through the motor. The feedback mechanism produces an error voltage that corresponds to the current error, and applies the voltage to a control driver. The control driver then controls the motor, based on the error voltage, in either a PWM or linear mode. By sharing a common core, the switching time between modes is improved. Furthermore, the output current error between modes is reduced.

Feedback control system and method

Provided herein are gap detection and compensation schemes for timing alignment systems. In certain embodiments, a timing alignment system includes a detector that generates one or more loop control signals based on comparing a reference clock signal to a feedback clock signal, a loop filter having a loop voltage that is adjusted based on the one or more loop control signals, and a gap detection and compensation circuit that processes the one or more loop control signals to detect a gap in at least one of the reference clock signal or the feedback clock signal. In response to detecting the gap, the gap detection and compensation circuit modifies the one or more loop control signals to provide an adjustment to the loop voltage.

Timing alignment systems with gap detection and compensation

A low dropout voltage regulator (LDO) includes first and second amplifiers and a current mirror. The first amplifier includes a first input receiving a reference voltage and a second input receiving a voltage proportional to an output of the LDO. The current mirror includes an input current at a first end of the current mirror to an output current at a second end of the current mirror, the input current controlled by an output of the first amplifier and the output current being supplied to the output of the LDO. The second amplifier includes a first input coupled to the first end of the current mirror and a second input coupled to the second end of the current mirror.

High power supply rejection ratio (PSRR) and low dropout regulator

A reference voltage generator circuit may include at least one MOS transistor and at least one bipolar transistor coupled together to provide an electrical path from an input reference potential to an output of the generator circuit. The electrical path may extend through a gate-to-source path of the MOS transistor and further through a base-to-emitter path of the bipolar transistor. The MOS transistor may be biased by a bias current that is proportional to T&#xb7;&#x3bc;(T), where T represents absolute temperature and &#x3bc;(T) represents mobility of a MOS transistor in the bias current generator. Optionally, the reference voltage generator may include N MOS and M multiple bipolar transistors (N&#x2267;1, M&#x2267;1), and the output reference voltage may be N*V+M*Vas compared to the input reference potential.

Reference voltage generators for integrated circuits

A method and a circuit for increasing a resolution of a digitally controlled oscillator include controlling the oscillator so that an output signal of the oscillator varies between semi-periods having a first frequency and semi-periods having a second frequency. The method and circuit further include applying the output signal of the oscillator as an input to a divider to obtain a divided signal. A frequency of at least one semi-period of the divided signal is a function of both an oscillator semi-period having the first frequency and an oscillator semi-period having the second frequency.

Method and circuit for increasing the resolution of a digitally controlled oscillator

An apparatus, system and method for controlling drive patterns is disclosed. A digital engine for controlling drive patterns may include a profile controller to program characteristics of one or more drive patterns for one or more piezoelectric actuators. The digital engine may further include a register array to store profile information for the one or more drive patterns. Each drive pattern may comprise a plurality of pulses with each pulse having a slope. The digital engine may also include a digital pattern generator to generate the one or more drive patterns based upon the profile information stored in the register array. The digital engine may further include a slope shaping circuit to modify one or more signals based upon an input from the digital pattern generator.

Integrated PWM slope control driving mechanism for gradually delivering energy to a capacitive load

A detection circuit is coupled to an output terminal of a driver circuit. The detection circuit includes a comparator to compare a signal at the output terminal to a reference signal corresponding to a signal that would be generated if a capacitive load having a relatively high capacitance value were connected to the output terminal. Output of the comparator is sampled at a predetermined time after the driver circuit provides the drive signal. An error signal is generated when the sampled output indicates that the capacitive load having the relatively high capacitance value is actually connected to the output terminal.

Protection circuit for driving capacitive loads

A system for a Class AB Amplifier output stage that includes a first push pull system connected to an output terminal including a first driving transistor coupled to the output terminal and a second push pull system connected to the output terminal including a second driving transistor coupled to the output terminal. The amplifier also includes a current mode amplifier where the current mode amplifier's output is coupled to the first driving transistor's gate. The amplifier further includes a pair of resistors, a first resistor coupled to a first input terminal of the current mode amplifier, a second resistor coupled to a second input terminal of the current mode amplifier and coupled to the second driving transistor.

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El Puig, Spain

Alberto Marinas