Stmicroelectronics S.r.l.

Alberto Jose' Di Martino

Gianbattista Lo Giudice

Giovanni Matranga

Rosario Roberto Grasso

Antonino Conte

Nicolas Demange

Enrico Castaldo

Daniele Zompi

A method for erasing non-volatile memory including applying a first voltage pulse to a non-volatile memory cell to perform a first erase operation of the non-volatile memory cell and determining that a threshold voltage of the non-volatile memory cell is greater than a test voltage. The method further comprising updating a dedicated memory location with a value; and checking the non-volatile memory cell to determine whether the threshold voltage of the non-volatile memory cell is less than an erase-verify voltage to verify that the first erase operation has been performed successfully.

Methods and devices for erasing non-volatile memory

A method of operating a non-volatile memory including having a first set of non-volatile memory cells and a second set of non-volatile memory cells. The first set of non-volatile memory cells and second set of non-volatile memory cells are associated with host addresses. Voltage levels are determined to erase the first and second sets of non-volatile memory cells. The first and second sets of non-volatile memory cells are disassociated from the host addresses. And, the first set of non-volatile memory cells is associated to another address based on the voltage level effective to erase the non-volatile memory cells.

Methods and devices for wear leveling

An amplifier circuit may include an input amplification stage comprising a first amplifier having first and second differential inputs and a first output, and a second amplifier having first and second differential inputs and a second output. The amplifier circuit also includes an output amplification stage having first and second inputs respectively coupled to the first and second outputs of the input amplification stage, and an output configured to supply an output voltage based upon the input voltage by an amplification factor. The amplifier circuit comprises a feedback stage with a common-mode control stage configured to implement a comparison between the first differential voltage and the second differential voltage, and a reference voltage, and generate respective regulation currents on the first and second inputs of the output amplification stage to compensate for a common-mode variation of the first differential voltage and the second differential voltage.

Amplifier circuit with static consumption control and corresponding control method

A biasing structure for a memory cell storage element, for setting an operating voltage at an accession electrode of the memory cell storage element. The biasing structure includes a biasing transistor coupled to the accession electrode and adapted to set the operating voltage based on a biasing voltage received at a control electrode of the biasing transistor, and a biasing voltage generator for generating the biasing voltage. The biasing voltage generator includes a feedback voltage regulation structure adapted track changes in a threshold voltage of the biasing transistor, so as to keep the operating voltage at the accession electrode of the memory cell storage element substantially stable against operating condition changes.

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Palagonia, Italy

Alberto Jose' Di Martino