Motorola Corporation

Other

Alberto J Reyes

Sean C Tyler

Gary K Yeap

Daniel Snyder

Steven D Millman

Dana Mark Rigg

Roberto Rodriguez

Sleiman N Chamoun

James P Garvey

Karen S Ramondetta

Jamel Valdes

Emilio Castro

Hongyu Xie

Dinesh D Gaitonde

The present invention is a power line cut-out switch used in power transmission system comprising a base member having a vertical extension member perpendicularly attached thereon that secures a mechanical jumper used when transferring power lines from one electrical post to another. The vertical member can include a mushroom top member to further secure the mechanical jumper. The mechanical jumper is mounted to the vertical extension member to provide a stable and secure point of engagement when transferring power lines. This avoids electrocution to workers by no longer having to connect the mechanical jumper to flimsy solid jumpers and helps provide more uninterrupted power supply to consumers when installing new posts or shifting old posts to a new location.

Powerline cutout switch improvement

A method (100) and apparatus (600) estimates power of an architectural design. Power functions are generated (step 102) for standard components (20) by synthesizing to a power-measurable implementation (step 202). A behavioral description is simulated (step 106) to produce switching activity and then parsed (step 108) to compute power from power functions of instantiated standard components (steps 109, 114, 118) from switching activity (step 116). Behavioral operations are parsed (step 108) into short and long blocks based on the number of operations. Short blocks are precompiled (step 110) to produce an RTL implementation including standard components. Power is estimated from switching activity at ports and inferred nodes (step 420). Long blocks are synthesized to produce power-measurable implementations (step 112). Power is estimated with a power function from weighted switching activity at each input (steps 508, 512-514).

Architectural power estimation method and apparatus

A method of selecting device (14-16, 18-24, 28-30) threshold voltages for high speed and low overall power involves identifying (42) the critical paths by predetermined timing criteria. All transistors have an initial, typically high, threshold voltage (40). Transistors outside the critical paths keep the initial high threshold voltages to minimize static power drain. The transistors in the critical path are selected (43) according to a predetermined sorting function to have a low threshold voltage and thereby switch faster. Although the lower threshold voltage devices consume more static power in standby mode, the power drain is accepted as a trade-off in favor of increased speed through the critical path. The supply voltage is reduced to minimize dynamic power. The integrated circuit is thus optimized to run at a higher frequency with lower overall power consumption.

Method of selecting device threshold voltages for high speed and low

A method of generating power vectors to calculate power dissipation for a circuit is provided. The circuit includes both combinational logic and sequential logic circuits. The method includes removing all sequential logic circuits from the circuit. Boolean equations that describe the logical operation of the combinational logic of the circuit cells are generated. Power vectors are generated from the Boolean equations corresponding to internal and output transitions which dissipate power in the circuit. Redundant power vectors are then eliminated. The power vectors are then analyzed for 'consistent' behavior with the sequential logic circuits. Operation of sequential logic circuits follow an ordered or defined sequence of events. Power vectors that are 'inconsistent' with the operation of the sequential logic circuits are eliminated. The remaining power vectors are used to simulate the power dissipation of the circuit.

Method of generating power vectors for circuit power dissipation

A method of generating power vectors to calculate power dissipation for a circuit cell is provided. The method involves formulating the Boolean equations (30) that describe the logical operation for a circuit cell (10). Primitive power vectors that cause an output to transition are generated (32) using Boolean difference functions. Internal power vectors that cause an internal node to transition without transitioning the output are generated (34) using Boolean difference functions. Static power vectors with all possible steady state inputs are also generated (36). The power vectors are minimized (38) to eliminate redundant vectors. The resulting power vectors can be used in a circuit simulation in evaluating (40) the power dissipation of a designed logic circuit.

Method of generating power vectors for cell power dissipation simulation

A low power flip-flop circuit is disclosed including a clocked flip-flop (10) and switching circuit (40, 60) with control inputs coupled to the data input and data output of the flip-flop to determine whether or not the data input to the flip-flop is changing. Any clock pulse during periods when the data input is not changing consumes power without providing a useful function. The switching circuit passes clock pulses to a clock input of the flip-flop only when new data is present to be latched into the flip-flop, i.e. data input state and data output state disagree. The switching circuit blocks clock pulses to the flip-flop when the data to the flip-flop is not changing and thereby saves power consumption.

Growing community of inventors

Phoenix, AZ, United States of America

Alberto J Reyes