Sgs-thomson Microelectronics S.r.l.

Sgs-thomson Microelectronics Limited

Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno

Alberto Gola

Giona Fucili

Roberto Gariboldi

Annamaria Rossi

Lorenzo Papillo

Gianluigi Pessina

Andrea Pasquino

Marco Pio Demicheli

Aldo Vittorio Novelli

Patrizia Milazzo

Fabrizio Stefani

Angelo Alzati

Marcello Leone

A successive approximation shift register without redundancy for a finite-state machine of the sequential type, is also effective to store the machine states. The shift register comprises a chain of logic circuits of the bistable type (FF0,FF1, . . . ) having an input stage with selectable signal inputs which are feedback connected through logic OR gate circuits (OR0,OR1, . . . ,OR6).

Successive approximation and shift register without redundancy

A sense and protection circuit against short circuits for digital outputs, comprising a logic gating circuit of the exclusive OR type (EX1) which has a first input terminal connected to a signal input node (IN) and an output terminal which is connected to an input terminal of a signal level shifter output stage (B). A second logic gating circuit of the exclusive OR type (EX2) has a first input terminal connected to the input node (IN) and a second input terminal connected, through an inverting circuit (IN1), to an output terminal (OUT) of the output stage (B). A second input terminal of the first logic gate circuit is coupled to an output terminal of the second logic gate circuit through a comparator circuit (SCH1) and a delay circuit means (C,R,D).

Circuit for detection and protection against short circuits for digital

A flip-flop of the D type capable of loading data asynchronously and comprising two latches, a master and a slave one, connected in series with each other, is characterized in that each of these comprises an interface and selection circuit for input signals transferable in either the synchronous or the asynchronous manner, and a logic gate circuit which is input such signals and, in an asynchronous manner, control signals effective to establish the latch own states.

D flip-flop having asynchronous data loading

A power-on reset circuit which employs a supply voltage sensing branch for triggering a first inverter of a pair of cascaded inverters. The intrinsic static consumption of such a POR circuit is strongly reduced by employing a current generator, which is automatically forced to deliver a reduced current during the operation of the integrated circuit, for biasing two transistors functionally connected in said voltage sensing branch into a subthreshold operating condition.

Power-on reset circuit having a low static power consumption

A bias structure for an integrated circuit including first and second transistors having emitter terminals coupled respectively to the supply and to a terminal of a resistor whose potential, under certain operating conditions of the circuit, exceeds the supply voltage; base terminals connected to each other and to a current source; and collector terminals connected electrically (12) to an epitaxial tub housing the resistor. A resistor is preferably provided between the two collectors, so that, when the potential of the terminal of the resistor exceeds the supply voltage, the second transistor saturates and maintains the epitaxial tub of the resistor at a potential close to that of the resistor terminal, thus preventing the parasitic diode formed between the resistor and the epitaxial tub from being switched on.

Epitaxial tub bias structure for integrated circuits

An output stage with a protection circuit against negative overvoltage at its output terminal, having a transistor with collector output and with the emitter connected to a reference voltage line; a diode for protection against negative overvoltages present on the output is arranged between the collector and the output of the stage. In order to give the output of the stage a presettable minimum voltage level, the reference voltage line is set to a preset voltage which differs from the ground voltage. For this purpose, the circuit comprises an operational amplifier in a voltage-follower configuration, the output whereof is connected to the reference voltage line, a diode which is connected between the ground and the non-inverting terminal of the operational amplifier, and a current source which is connected between the non-inverting input of the operational amplifier and a negative supply line.

Negative overvoltage protection circuit, in particular for output stages

A negative overvoltage protection circuit for an insulated vertical PNP transistor the emitter whereof defines the input, the collector whereof defines the output and the base whereof is connected to an NPN driving transistor. In order to maximally extend the negative overvoltage which can be applied to the output, the protection circuit comprises an output voltage sensor, a voltage reference, a comparator which is connected in input to the voltage reference and to the sensor and generates in output an activation signal when the output voltage of the PNP transistor becomes smaller than the reference, a switch which is controlled by the comparator to switch off the NPN driving transistor upon the reception of the activation signal and a low-impedance circuit which is connected between the emitter and the base of the insulated vertical PNP transistor and is activated by the activation signal, in a manner suitable for bringing the insulated vertical PNP transistor practically to BV.sub.CBO.

Negative overvoltage protection circuit for insulated vertical PNP

An electronic comparator circuit having a high speed during switch phase and combining the advantages of bipolar technology with those of CMOS technology. The circuit consists of a differential stage input circuit having a differential pair of bipolar transistors forming its outputs. The output stage contains a pair of MOS transistors having gate electrodes in common. The pair of MOS transistors is connected on one side to the outputs of the input portion and on the other side to a positive supply pole via a current mirror circuit. The output contains another pair of MOS transistors with gate electrodes in common connected between the outputs of the input portion and ground. The drain electrode of the first pair of MOS transistors forms the output for the comparator.

Comparator circuit implemented in the bipolar and MOS technology

The pilot circuit comprises an R-C network consisting of a condenser inserted between a gate terminal of the MOS transistor and ground and a resistance for charging said condenser. In parallel with the resistance there is placed an SCR circuit with associated threshold circuit which permits firing of the SCR circuit when the charge voltage of the condenser reaches a preset threshold.

Pilot circuit with integrated circuit with preset firing delay for MOS

An improved power stage with increased output dynamics. The stage comprises a power amplifier having a first inverting input, a second non-inverting input, an output to be connected to a load and a feedback network comprising a first resistor connected between the inverting input and the output of the power amplifier and a second resistor connected between the first inverting input and a first line set to a first reference voltage by means of a voltage generator with preset values. The stage furthermore comprises an input voltage generator generating an input voltage signal to be amplified and connected between the second non-inverting input and a second line set to a second reference voltage different from said first reference voltage. In order to increase the output dynamics, in particular in the case of low power supply voltage, said voltage generator arranged between the second resistor and said input voltage generator, and generating a voltage which is variable in inverse proportion to the input voltage signal, with respect to the second reference voltage.

Power stage with increased output dynamics

A circuit for limiting the transient overvoltage across a power transistor connected in series with an inductive load between a supply rail and a ground rail of the circuit and operated to switch ON-OFF the inductive load utilizes a comparator circuit for switching-ON again the power transistor in order to discharge the energy stored in the load's inductance. The voltage across the power transistor is sensed by a first voltage divider, while a reference voltage is obtained by a second voltage divider connected between the supply and ground. The circuit is practically insensitive to temperature and to variations of the supply voltage and is easily implemented.

Active overvoltage control for inductive load driving

A broadband amplifier comprising insulated collector vertical pnp transistors, a circuit device effective to improve frequency response, and a final stage comprising a so-called complementary pair formed of an npn transistor and a pnp transistor having emitters connected to each other and to an epitaxial layer n of the insulated collector vertical pnp transistor incorporated in the gain circuit of said amplifiers. The complementary pair afford minimization of the junction parasitic capacitances of the aforesaid vertical pnp transistor.

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Broni, Italy

Alberto Gola