Qualcomm Incorporated

Alberto Cicalini

Peter Han Lien

Mohammad Ali Tassoudji

Sang-June Park

Jorge Fabrega Sanchez

Kevin Hsi-Huai Wang

Gurkanwal Singh Sahota

Mohammad Bagher Vahid Far

Aristotele Hadjichristos

Jesse Aaron Richmond

Cheng-Han Wang

Gary John Ballantyne

Puay Hoe See

Darryl Sheldon Jessie

Faramarz Sabouri

Thinh Cat Nguyen

Neil Burns

Taesik Yang

Jeongil Jay Kim

Dongjiang Qiao

Julio Zegarra

Gary Lee Brown, Jr

Sean Oak

Eric Lunzer

Gary L Brown

A device that includes a first board, a second board, and coaxial cable coupled to the first board and the second board. The coaxial cable includes a multi-line coaxial cable configured to provide at least two electrical paths for electrical currents between the first board and the second board. A first plug is coupled to the first board. A second plug is coupled to the second board. The coaxial cable includes a first receptacle and a second receptacle. The first receptacle is configured to couple to the first plug. The second receptacle is configured to couple to the second plug. The coaxial cable is configured to provide (i) a first electrical path for a first electrical current between the first board and the second board, and (ii) a second electrical path for a second electrical current between the first board and the second board.

Multi-line interface for board and substrate

Apparatus, methods, and computer-readable media for implementing a display-side antenna are disclosed herein. An example apparatus for wireless communication includes a housing and a display device supported by the housing. The example display device includes at least a glass cover and a panel positioned between the glass cover and an internal surface of the housing. The panel may be configured to output graphical content for presentment on the glass cover via pixels arranged within a visible area of the panel. The example apparatus also includes an antenna array. The antenna array may be configured to facilitate wireless communication at the apparatus. The antenna array may be positioned to overlap a portion of the visible area of the panel and configured to allow graphical content output by the panel to display on the glass cover at the overlapped portion of the visible area.

Display-side antenna

An integrated millimeter wave antenna module may include at least one antenna array directly connected to a wiring board with a flexible printed circuit without any additional connectors. The integrated module may include an antenna, a flexible printed circuit attached to the antenna on one end and a wiring board on the other end.

Integrated antenna module

An electronic device includes a first antenna, a second antenna, and a device cover. The first antenna may be configured to transmit or receive signals at a first frequency, and the second antenna may be configured to transmit or receive signals at a second frequency. The device cover may be configured to enclose at least a portion of the device, the and may have a first thickness in a first area and a second thickness in a second area. The first area may be substantially aligned with a boresight of the first antenna, and the second area may be substantially aligned with a boresight of the second antenna. The first thickness may be different than the second thickness.

Antenna and device configurations

A method, an apparatus, and a system product for mixing radio frequency signals are provided. In one aspect, the apparatus is configured to perform switching of switches based on first, second, third, and fourth phased half duty clock signals. The apparatus convolves a differential input signal on a differential input port with the first, second, third, and fourth phased half duty cycle clock signals to concurrently generate a differential in-phase output signal and a differential quadrature-phase output signal on a dual differential output port. The first, second, third, and fourth phased half duty cycle clock signals are of the same frequency and out of phase by a multiple of ninety degrees with respect to each other.

Fully I/Q balanced quadrature radio frequency mixer with low noise and low conversion loss

Techniques for providing a transceiver with a sliding intermediate frequency (IF). In an aspect, a PLL generates a single local oscillator (LO) signal used for both up-conversion by a transmit (TX) signal path and down-conversion by a receive (RX) signal path, wherein the LO frequency is chosen as the TX carrier frequency. As the TX and RX carrier frequencies may generally differ by a variable amount, the RX signal path utilizing the (TX) LO frequency for down-conversion may be characterized as having a 'sliding' IF. To accommodate the sliding IF receiver architecture, specific processing functions such as charge sampling, discrete-time analog band-pass filtering, and sub-sampling analog-to-digital conversion (ADC) are described.

Sliding if transceiver architecture

Exemplary embodiments disclosed are directed to power and impedance measurement circuits that may be used to measure power and/or impedance are described. A measurement circuit may include a sensor and a computation unit. The sensor may sense (i) a first voltage signal across a series circuit coupled to a load to obtain a first sensed signal and (ii) a second voltage signal at a designated end of the series circuit to obtain a second sensed signal. The sensor may mix (i) a first version of the first sensed signal with a first version of the second sensed signal to obtain a first sensor output and (ii) a second version of the first sensed signal with a second version of the second sensed signal to obtain a second sensor output. The computation unit may determine the impedance and/or delivered power at the designated end of the series circuit based on the sensor outputs.

Power and impedance measurement circuits for a wireless communication device

Disclosed are frequency dividers, methods, apparatus, and other implementations, including a frequency divider that includes at least one input line to deliver at least one signal with a first frequency, a divider stage comprising multiple divider active components to produce output signals each with a second frequency equal to substantially half the first frequency, and an input stage electrically coupled to the divider stage to enable operation of the divider stage, the input stage including multiple additional active components. Each of the output signals is electrically coupled to an input of a different corresponding component of the multiple additional active components to electrically actuate the respective different corresponding components such that each of the multiple additional active components is periodically in an ON state while during the same time at least another of the multiple additional active components of the input stage is in an OFF state.

Dynamic divide by 2 with 25% duty cycle output waveforms

A parallel path frequency divider (PPFD) includes a low power frequency divider and a high speed latch. A first portion of an oscillating input signal present on an input node of the PPFD is communicated to the divider and a second portion is communicated to the latch. The divider generates a frequency divided enable signal that is communicated to the latch. The latch generates a divided down output signal based on the oscillating input signal and the enable signal. The output signal is insensitive to phase noise present on the enable signal as long as the phase noise on the enable signal is less than one-half of the period of oscillation of the oscillating input signal. Because the noise generated by the low power frequency divider is not propagated to the output signal generated by the PPFD, the PPFD generates low noise, frequency divided signals with relatively low power consumption.

Parallel path frequency divider circuit

In one embodiment of the invention, a method for convolution of signals is disclosed including generating four phased half duty cycle clocks each being out of phase by a multiple of ninety degrees from the others; coupling the four phased half duty cycle clocks into a four phase half duty cycle mixer; and switching switches in the four phase half duty cycle mixer in response to the four phased half duty cycle clocks to convolve a differential input signal with the four phased half duty cycle clocks to concurrently generate a differential in-phase output signal and a differential quadrature-phase output signal on a dual differential output port.

Quadrature radio frequency mixer with low noise and low conversion loss

During an ESD event, an ESD current flows from a ground node of a first ESD protection circuit and out of an integrated circuit to a terminal of a package that houses the integrated circuit. To improve ESD performance, a second ESD protection circuit is provided. A diode of the second ESD protection circuit is coupled between the ground node and the body of an input transistor of a Low Noise Amplifier (LNA). If the voltage on the ground node changes quickly during an ESD event (for example, due to a current spike flowing across a wire bond), then the diode charges the body of the transistor, thereby preventing a large gate-to-body voltage from developing across transistor. In some embodiments, another ground bond pad is provided and the second ESD protection circuit includes other diodes that charge or discharge other nodes during the ESD event to prevent transistor damage.

ESD protection for field effect transistors of analog input circuits

A bias generator comprises a first transistor and a second transistor having a control port connected to a control port of the first transistor and to an input port of the second transistor, where a second current through the second transistor is greater than a first current through the first transistor. The current through the bias generator is minimized by providing the different currents through the transistors having a similar size.

Bias generator with reduced current consumption

A two-step tuning process for resistors and capacitors in an integrated circuit is described. In the first step of the tuning process, an on-chip adjustable resistor is tuned based on an external resistor to obtain a tuned resistor. The value of the tuned resistor is accurate to within a target percentage determined by the external resistor and the design of the adjustable resistor. In the second step, an adjustable capacitor is tuned based on the tuned resistor and an accurate clock to obtain a tuned capacitor having an accurate value. The adjustable capacitor may be tuned such that an RC time constant for the tuned resistor and the tune capacitor is accurate to within a target percentage determined by the accurate clock and the design of the adjustable capacitor. The resistors and capacitors of other circuits on the integrated circuit may be adjusted based on the tuned resistor and the tuned capacitor, respectively.

Growing community of inventors

San Diego, CA, United States of America

Alberto Cicalini