International Business Machines Corporation

Albert Y Chang

Mark F Mergen

John Cocke

John Thomas O'Quin, Ii

John C O'Quin, Iii

Marc Alan Auslander

George Radin

Robert K Montoye

Gus Wai-Yan Yeung

Mark D Rogers

Thomas R Puzak

Edward John Silha

Larry Edward Thatcher

Stephen P Morgan

Grover Herbert Neuman

James O Nicholson

Todd A Smith

Algirdas J Gruodis

Joseph R Cavaliere

Richard R Oehler

Dale E Hoffman

Amal A Shaheen-Gouda

Mark Jay Charney

Daniel E Skooglund

George A Lerom

Rocco J Robortaccio

Robert Morris Meade

Punit J Pandya

As a program is replaced by the operating system running within a microprocessor, only those entries associated with the replaced program and resident within effective-to-real address translation units will be replaced. Those entries within the effective-to-real address translation units associated with the operating system and shared libraries, and any other software units operating within the microprocessor will not be invalidated.

System and method for invalidating an entry in a translation unit

A method for storing information in a computer memory system includes maintaining an M,level storage system including an M,level data store for storing data, an M,level full directory for storing a set of tags corresponding to the data, and an M,level partial directory for storing a subset of the tags. The partial directory is accessible faster than the full directory. Upon an M-1 level miss corresponding to a request for data, a congruence class corresponding to the request is fetched from the partial directory when it is present therein; otherwise, it is fetched from the full directory. The requested data is retrieved from the data store when it is present in the congruence class; otherwise, it is retrieved from a next level of the memory system. The tags in the partial directory may be full tags, partial tags, or a combination thereof.

Methods for caching cache tags

A memory address translation and related control system for performing the dual functions of converting virtual memory addresses generated by the CPU into real memory addresses in a highly efficient and versatile manner and for controlling certain memory functions such as journalling. The address translation function comprises two steps, the first comprising converting the virtual address into a second virtual address or an effective address and finally the step of converting the effective address into a real memory address. The first step utilizes a set of special registers addressable by a small field to the CPU generated virtual address which converts the virtual address into an expanded form. The second or effective address is then used as the subject of the second or address translation step. To greatly enhance the translation of frequently used virtual addresses, a special set of translation tables referred to herein as a Translation Look-Aside, Buffer (TLB) contain current effective to real address translations for use where frequently referenced addresses are requested. The TLBs are addressed using a subset of the effective address whereupon the contents of the addressed TLB is examined for a match with the effective address. If the addresses match a successful address translation is possible and the real address stored in the address field of the TLB is available for system use. If the desired effective address is not present in the TLB, the page frame tables stored in main memory are accessed and searched for the desired effective address and if found the associated real address is accessed. Further a special data field is provided in both the TLBs and the page frame tables in main memory wherein a bit is provided for each line in the referenced page at a given effective to real address translation which bits may be used to indicate when a line of data has been accessed or altered.

Virtual memory address translation mechanism with controlled data persistence

A first group of memory locations stores information. The first group is arranged into multiple congruence classes of memory locations. The congruence classes include a first congruence class having more than one memory location. A second group of memory locations stores information from the first group of memory locations. Directory locations store information relating the first and second groups of memory locations. The directory locations include a first directory location able to store information relating a particular one of the second group of memory locations to any memory location of more than one of the congruence classes including the first congruence class.

Circuitry and method for relating first and second memory locations

A cache for use with input/output devices attached to an input/output bus. Requests for access to system memory by an input/output device pass through the cache. Access authority is checked to determine whether an input/output device is authorized to access that particular page. If it is not, access is denied. Each input/output device has access to a portion of the cache, so that activity by one device will not interfere with activity by another.

I/O cache controller containing a buffer memory partitioned into lines

A data processing method for storing groups of related information in a storage subsystem of a data processing system in which the storage subsystem includes one or more storage devices having a plurality of block addressable storage locations (blocks or sectors) each of which stores a predetermined fixed number of bytes of said information. The method includes the step of establishing allocatable increments of storage, called physical partitions, which comprise a predetermined number of contiguous addressable blocks, and initially allocating, in response to a request to the operating system, a preselected number of partitions for each group of related information, where the partitions in each group are not necessarily physically contiguous and where the number that is selected is the minimum number of partitions required to store the group of related information. The method further includes the step of automatically allocating one or more additional partitions, located physically on any device, to a previously allocated group of related partitions, dynamically in response to another request of the operating system. A group of partitions that have been allocated to store a group of related information, such as individual files that are related in a hierarchical file system, is called a 'Logical Volume'. Logical Volumes may be further combined for administration and data management reasons into a 'Volume Group'.

Data processing method to create virtual disks from non-contiguous

A driver circuit is disclosed for use in testing bi-directional transceiver semiconductor products using a minimum of time and number of product accessing pins. The driver includes a pair of controllable amplitude current sources whose output currents are selectably switched into or partially away from the commonly connected emitters of a current switch. The current switch is energized by a variable voltage source and produces the output test voltage.

Driver circuit for testing bi-directional transceiver semiconductor

A method and apparatus for controlling access to data blocks stored by addresses in a memory and concurrently accessible by a plurality of transactions is provided. The method includes the steps of receiving an address of a data block to be accessed by a first transaction, deriving from the address an access table entry corresponding to the data block where the entry includes lock data that governs access to the data block, and providing the access if permitted by the lock data, or providing the access, if not permitted by the lock data, and recording the occurrence of the access in the lock data.

Memory controller for protected memory with automatic access granting

In a distributed environment several data processing systems are interconnected across a network system. A distributed services program installed on the systems in the network allows the processors to access data files distributed across the various nodes of the network without regard to the location of the data file in the network. The processing system accessing file, referred to as the client processing system, utilizes a client cache within its operating system to store the data file. Utilizing the client cache minimizes the number of reads and writes that must go over the network to the server processing system where the file physically resides. The system and method of this invention prevents a process in the client processing system from accessing data in the client cache that has been modified at another node in the network. The blocks of data in the client cache are tested for validity in the client processing system by using modification times as measured by the server processing system. If the cache data blocks are determined to be valid, the data blocks are determined to be invalid, the data blocks are discarded, and the file is accessed from the server processing system.

System and method for using cached data at a local node after re-opening

A method to logically serialize a plurality of independent system events in a virtual memory data processing system. Each event causes interrupt servicing routines to be executed and requires data structures that record the status of virtual pages to be updated. The system events include the interrupt that is generated as a result of a page fault, the interrupt that is generated as a result of a paging I/O completion operation that resolves a page fault, and lastly interrupts generated in response to a supervisory call to a paging service.

Method to control paging subsystem processing in a virtual memory data

A simultaneous bi-directional transceiver is described. The transceiver comprises two circuits which are disposed at opposite ends of an interchip cable. In response to the application of digital data signals to these circuits, they generate a trilevel voltage at the ends of the interchip cable. Then, in each circuit, a first input to a differential amplifier is generated from the trilevel voltage by a level shifter comprising a first diode and a first constant current sink and a second input to the differential amplifier is derived from the digital data input signal applied to that circuit by a level shifter comprising a second diode and a second constant current source. Finally, the transceiver outputs are generated from the differential amplifier outputs.

Bi-directional transceiver circuit

Virtual memory address translation mechanism with controlled data

An improved current switch emitter follower (CSEF) latch has reduced 'noise' in the output signal from equal and opposite operation of the output transistors. The improvement resides in dotting the collector resistors of the input transistors in each current switch with a common shift resistor. The dotted collector resistors control the output transistors whereby one turns on and the other turns off with little change in output signal level as clock signals change to the input transistor.

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Poughkeepsie, NY, United States of America

Albert Y Chang