Samplify Systems, Inc.

Altera Corporation

Integrated Device Technology, Inc.

Command Audio Corporation

Anacode Labs, Inc.

Other

White Eagle Sonic Technologies, Inc.

Simplify Systems, Inc.

Albert William Wegener

Thomas Linden

Yi Ling

Edward J Costello

Jonathan Voichick

Serge Swerdlow

Allan Michael Evans

Michael V Nanevicz

Carl R Crawford

William J Loewenthal, Jr

Eric X Wen

Orlando Martinez

John Schoellerman

Donald F Bogue

Massively parallel, block-based encoding and decoding technology that includes an encoded block format uses a plurality of processing cores to perform block-based encoding and decoding operations. The encoded block format includes a header and a payload. The encoded block format's headers represent unique single-Byte and multi-Byte event parameters that occur in the original data block from which each encoded block was generated. The encoded block format's payloads represent a sequence of single-Byte and multi-Byte events using tokens that associate each event with its corresponding parameter(s). Metadata can include an array of encoded block sizes that support random access.

Parallel, block-based data encoding and decoding using multiple computational units

A block-oriented lossless decompressor is used to decode encoded data fetched from storage that is subsequently transferred across a network in encoded (compressed) form. In examples described herein, applications executing at network nodes send GET requests, or similar messages, to storage systems, which can return compressed data this is decompressed in an intermediate node (between the storage node and the app), and can return compressed data that is decoded in the same network node in which the requesting application is running.

Accelerated data center transfers

A combination of a block-oriented encoder and decoder with a modified dataset identifier that is associated with an encoded block size are used to perform block-based encoding and decoding operations. The encoding process may generate optional metadata that includes an array of encoded block sizes to support random access into the stream or group of encoded blocks during the decoding process. The modified dataset identifier associates the original dataset identifier with the block size used by the encoder.

Storage access interface to an encoded storage system

Configurable compression and decompression of waveform data in a multi-core processing environment improves the efficiency of data transfer between cores and conserves data storage resources. In waveform data processing systems, input, intermediate, and output waveform data are often exchanged between cores and between cores and off-chip memory. At each core, a single configurable compressor and a single configurable decompressor can be configured to compress and to decompress integer or floating-point waveform data. At the memory controller, a configurable compressor compresses integer or floating-point waveform data for transfer to off-chip memory in compressed packets and a configurable decompressor decompresses compressed packets received from the off-chip memory. Compression reduces the memory or storage required to retain waveform data in a semiconductor or magnetic memory. Compression reduces both the latency and the bandwidth required to exchange waveform data. This abstract does not limit the scope of the invention as described in the claims.

Enhanced multi-processor waveform data exchange using compression and decompression

An execution unit configured for compression and decompression of numerical data utilizing single instruction, multiple data (SIMD) instructions is described. The numerical data includes integer and floating-point samples. Compression supports three encoding modes: lossless, fixed-rate, and fixed-quality. SIMD instructions for compression operations may include attenuation, derivative calculations, bit packing to form compressed packets, header generation for the packets, and packed array output operations. SIMD instructions for decompression may include packed array input operations, header recovery, decoder control, bit unpacking, integration, and amplification. Compression and decompression may be implemented in a microprocessor, digital signal processor, field-programmable gate array, application-specific integrated circuit, system-on-chip, or graphics processor, using SIMD instructions. Compression and decompression of numerical data can reduce memory, networking, and storage bottlenecks. This abstract does not limit the scope of the invention as described in the claims.

SIMD instructions for data compression and decompression

Compression and decompression of numerical data utilizing single instruction, multiple data (SIMD) instructions is described. The numerical data includes integer and floating-point samples. Compression supports three encoding modes: lossless, fixed-rate, and fixed-quality. SIMD instructions for compression operations may include attenuation, derivative calculations, bit packing to form compressed packets, header generation for the packets, and packed array output operations. SIMD instructions for decompression may include packed array input operations, header recovery, decoder control, bit unpacking, integration, and amplification. Compression and decompression may be implemented in a microprocessor, digital signal processor, field-programmable gate array, application-specific integrated circuit, system-on-chip, or graphics processor, using SIMD instructions. Compression and decompression of numerical data can reduce memory, networking, and storage bottlenecks. This abstract does not limit the scope of the invention as described in the claims.

Data compression and decompression using SIMD instructions

A signal compression method and apparatus for a base transceiver system (BTS) in a wireless communication network provides efficient transfer of compressed signal samples over serial data links in the system. For the uplink, an RF unit of the BTS compresses baseband signal samples resulting from analog to digital conversion of a received analog signal followed by digital downconversion. The compressed signal samples are transferred over the serial data link to the baseband processor then decompressed prior to normal signal processing. For the downlink, the baseband processor compresses baseband signal samples and transfers the compressed signal samples to the RF unit. The RF unit decompresses the compressed samples prior to digital upconversion and digital to analog conversion to form an analog signal for transmission over an antenna. Compression and decompression can be incorporated into operations of conventional base stations and distributed antenna systems, including OBSAI or CPRI compliant systems.

Compression of baseband signals in base transceiver system processors

Memory system operations are extended for a data processor by an application programming interface API, including a set of operations and parameters for the operations, which provides for data compression and decompression during or in conjunction with processes for moving data between memory elements of the memory system. The set of operations can be configured to use the parameters and perform the operations of the API. The API can support moves between memory having a first access latency, such as memory integrated on the same chip as a processor core, and memory having a second access latency that is longer than the first access latency, such as memory on a different integrated circuit than the processor core.

Processing system and method including data compression API

A method and apparatus for determining one or more compression parameters suitable to compress a class of signals, may include inputting a test data set, being representative of a data set to be compressed, characterizing the test data, selecting a compression algorithm, calculating a distortion level to be used in determining the compression ratio (or a compression ratio to be used in determining the distortion level), generating a computer implemented model for the test data, selecting a recommended operating point based on a computer implemented model, and determining compression parameters corresponding to the operating point. The compression parameters may subsequently be applied for configuration of compression applied to one or more production data sets that are similar to the test data. This abstract does not limit the scope of the invention as described in the claims.

Data compression profiler for configuration of compression

Compression and decompression of numerical data can apply to floating-point or integer samples. Floating-point samples are converted to integer samples and the integer samples are compressed and encoded to produce compressed data for compressed data packets. For decompression, the compressed data retrieved from compressed data packets are decompressed to produce decompressed integer samples. The decompressed integer samples may be converted to reconstruct floating-point samples. Adaptive architectures can be applied for integer compression and decompression using one or two FIFO buffers and one or two configurable adder/subtractors. Various parameters can adapt the operations of adaptive architectures as appropriate for different data characteristics. The parameters can be encoded for the compressed data packet. This abstract does not limit the scope of the invention as described in the claims.

Conversion and compression of floating-point and integer data

A raw format image representing an image received from an image capture device at an image data rate, can be compressed at least as fast as the image data rate (i.e. in real time) using compact and low cost components. The compressed image data can then be transferred across a chip-to-chip data channel to a memory system or to a host processor where it can be stored as compressed data. The host processor or other processor can read and decompress the compressed raw data and apply digital signal processing including industry-standard data compression or other image processing algorithms to the recovered raw format image without being constrained to real-time processing.

Raw format image data processing

In a distributed antenna system (DAS) and a local area network (LAN), a common communication infrastructure distributes data from radio-based and Internet-based sources. A radio equipment (RE) of the DAS interfaces to a LAN segment. For the downlink, a gateway maps radio signal data from a radio equipment controller (REC) and data packets from a switch to mixed-data frames using a radio data interface protocol for transmission in the DAS. At the RE, the signal data and data packets are retrieved from the mixed-data frames and provided to the air interface and LAN segment, respectively. For the uplink from the RE, the radio signal data from the air interface and the data packets from the LAN segment are mapped to mixed-data frames and transmitted to the gateway. The gateway retrieves the signal samples and data packets from the mixed-data frames for transfer to the REC and switch, respectively.

Transmission of multiprotocol data in a distributed antenna system

Compression of floating-point numbers is realized by comparing the exponents of the floating-point numbers to one or more exponent thresholds to classify the floating-point numbers and to apply different compression types to the different classes. Each class and compression type is associated with an indicator. An indicator array contains M indicators for M floating-point numbers. The position of the indicator in the indicator array corresponds to one of the floating-point numbers and the indicator value specifies the class and compression type. The floating-point number is encoded in accordance with the compression type for its class. A compressed data packet contains the indicator array and up to M encoded floating-point numbers. Decompression extracts the indicator array and the encoded floating-point numbers from the compressed data packet and decodes the encoded floating-point numbers in accordance with the compression type associated with the indicator value to form a reconstructed floating-point number.

Computationally efficient compression of floating-point data

Memory system operations are extended for a data processor by DMA, cache, or memory controller to include a DMA descriptor, including a set of operations and parameters for the operations, which provides for data compression and decompression during or in conjunction with processes for moving data between memory elements of the memory system. The set of operations can be configured to use the parameters and perform the operations of the DMA, cache, or memory controller. The DMA, cache, or memory controller can support moves between memory having a first access latency, such as memory integrated on the same chip as a processor core, and memory having a second access latency that is longer than the first access latency, such as memory on a different integrated circuit than the processor core.

Data compression for direct memory access transfers

Compression of exponents, mantissas and signs of floating-point numbers is described. Differences between exponents are encoded by exponent tokens selected from a code table. The mantissa is encoded to a mantissa token having a length based on the exponent. The signs are encoded directly or are compressed to produce fewer sign tokens. The exponent tokens, mantissa tokens and sign tokens are packed in a compressed data packet. Decompression decodes the exponent tokens using the code table. The decoded exponent difference is added to a previous reconstructed exponent to produce the reconstructed exponent. The reconstructed exponent is used to determine the length of the mantissa token. The mantissa token is decoded to form the reconstructed mantissa. The sign tokens provide the reconstructed signs or are decompressed to provide the reconstructed signs. The reconstructed sign, reconstructed exponent and reconstructed mantissa are combined to form a reconstructed floating-point number.

Growing community of inventors

Portola Valley, CA, United States of America

Albert William Wegener