Atmel Corporation

Microchip Technology Inc.

Simtek Corporation

Albert Weiner

Christian E Herdt

Daniel Joseph Russell

Suraj Sridhar

Lorenzo Bedarida

Simone Bartoli

John W Tiede

Daniel J Russell

Sridhar Devulapalli

Jeffrey S Hapke

Michael Klein

David A Kamp

Klaus J Dimmler

Some embodiments of the present disclosure relate to a system that may include a replaceable module and a user device. The replaceable module may include an element and a one-wire authentication element in parallel with the element. The user device may be configured for operable coupling with the replaceable module. The user device may include a power source configured to provide power to the element, an authentication unit configured to perform a verification process for verifying authenticity of the replaceable module, and a signal conditioning unit arranged in a communication path between the one-wire authentication element and the authentication unit.

Interfacing with a one-wire device that is in parallel with a low-impedance element, and related systems and devices

A memory device, memory address decoder, a memory system and related method for memory attack detection are disclosed. An apparatus includes a memory decoder include multiple stages in a decoding path configured to generate a select signal from an input address signal, and fault detecting logic operably coupled with the memory decoder and configured to receive feedback signals distributed from the multiple stages indicative of a fault along the decoding path.

Memory device, memory address decoder, system, and related method for memory attack detection

An integrated circuit device is disclosed, which integrated circuit device comprises at least a first external contact, a second external contact, and an input stage, connected with the external contacts and being configured to provide an internal operating voltage when an external voltage is applied to the external contacts. To allow easier handling at manufacture, test, assembly, and end use, the internal operating voltage has a predefined polarity, which predefined polarity is independent of the polarity of the external voltage.

Symmetric input circuitry for IC in two-pin package

This specification describes an integrated circuit comprising: a single wire interface; a clock circuit configured to detect a voltage from the single wire interface and to generate a clock signal having a frequency that is based on the detected voltage; and a digital system coupled with the single wire interface and the clock circuit. The digital system is configured to: receive a data signal from the single wire interface; power the digital system using a power signal from the single wire interface; and perform one or more operations clocked by the clock signal.

Single wire system clock signal generation

In an embodiment, a memory system comprises a memory array having memory cells. A decoder is coupled to the memory array and configured to decode input address signals to generate memory cell selection signals. An encoder is configured to generate encoded selection signals based on the memory cell selection signals. In another embodiment, a method comprises: receiving by the decoder of the memory system input address signals, generating, by the decoder, selection signals for selecting a memory cell in the memory array, and generating, by an encoder, encoded selection signals based on the selection signals.

Memory system with encoding

A charge pump is incorporated into circuitry of an RFID tag. The charge pump takes advantage of an antenna voltage phase to eliminate the need for a charge pump clock generator. Placement of the charge pump in the RFID circuitry reduces the number of pump stages and eliminates drivers used in each pump stage. In some implementations, an RFID tag comprises antenna circuitry, including a tuned antenna, for receiving an RF signal. Voltage conversion circuitry in the RFID tag is coupled to the antenna circuitry and operable for converting a varying magnetic field produced in the antenna to a voltage source. A charge pump is coupled to output voltage signals of the antenna circuitry which provide the charge pump with a high starting reference voltage and a two phase pump clock.

Non-volatile memory charge pump for radio frequency identification (RFID) system

A low power sense amplifier is configured to sense the state of a memory cell (e.g., non-volatile memory cell) without the use of a reference current or direct current.

Low power sense amplifier for reading memory

A memory array has memory elements of identical topology or footprint arranged in rows and columns. Some of the memory elements are EEPROM cells and other memory elements are read only memory cells but all are made using a mask set having the same length and width dimensions. In the mask set for EEPROMs a principal mask is used for formation of a depletion implant. In the case of one type of read-only memory element, this mask is mainly blocked, leading to formation of a transistor with a non-conductive channel between source and drain. In the case of another read only memory element, the same mask is unblocked, leading to formation of a transistor with a highly conductive or almost shorted channel between source and drain. These two read only memory elements are designated as logic one and logic zero. By having rows of read-only memory elements with rows of EEPROMs on the same chip, a more versatile memory array chip may be built without sacrificing chip space.

Non-volatile transistor memory array incorporating read-only elements with single mask set

A self-adjusting PWM regulator which minimizes undershoot and overshoot conditions is disclosed. The regulator includes a charge pump, a voltage comparator circuit, and a latch circuit. The input of the voltage comparator circuit includes an output of the charge pump. The input of the latch circuit includes an output from the voltage comparator circuit. The latch circuit includes a pair of SR latches coupled to a pair of AND/OR gates. The latch circuit transmits a first signal to the charge pump to prevent an overshoot condition if the output from the voltage comparator circuit is in a first state, and transmits a second signal to prevent an undershoot condition if the output from the voltage comparator circuit is in a second state. This keeps the charge pump adjusted within the limits of its control.

Self-limiting pulse width modulation regulator

The present invention provides a non-volatile, static random access memory (nvSRAM) cell with a current limiting feature that prevents current that is provided to the cell or array of cells during a recall operation in which information is transferred from the non-volatile portion of the cell or array to the static random access memory portion of the cell or array from reaching a point that would be detrimental to the cell or array. The current limiting device is located between the nvSRAM cell or array of cells and ground. In one embodiment, the current limiting device includes a variable resistance and a device for modulating the resistance so that the resistance is high at the beginning of a recall operation and decreases thereafter.

Non-Volatile, static random access memory with current limiting

The present invention provides a computer memory device having a sleep mode characterized by extremely low current consumption and relatively large turn on delay. The invention includes circuitry for disabling current sinking elements internal to said device in response to a sleep signal. In one embodiment, the invention includes circuitry for disconnecting the bit lines and memory cell loads of a nonvolatile static random access memory (nvSRAM) array from a source of power in response to a sleep signal. This embodiment is capable of first transferring the data stored in a volatile portion of the array to a nonvolatile portion of the array before entering sleep mode to prevent loss of the data.

Growing community of inventors

Colorado Springs, CO, United States of America

Albert Weiner