International Business Machines Corporation

Thunderbird Technologies, Inc.

Albert W. Vinal

Albert W Vinal

Michael W Dennen

Earl Albert Cunningham

David A Thompson

William G Crouse

Lee S Rogers

A high saturation current, low leakage, Fermi threshold field effect transistor includes a predetermined minimum doping concentration of the source and drain facing the channel to maximize the saturation current of the transistor. Source and drain doping gradient regions between the source/drain and the channel, respectively, of thickness greater than 300.ANG. are also provided. The threshold voltage of the Fermi-FET may also be lowered from twice the Fermi potential of the substrate, while still maintaining zero static electric field in the channel perpendicular to the substrate, by increasing the doping concentration of the channel from that which produces a threshold voltage of twice the Fermi potential. By maintaining a predetermined channel depth, preferably about 600.ANG., the saturation current and threshold voltage may be independently varied by increasing the source/drain doping concentration facing the channel and by increasing the excess carrier concentration in the channel, respectively. A Fermi-FET having a gate insulator thickness of less than 120.ANG., and a channel length of less than about 1 .mu.m can thereby provide a P-channel saturation current of at least 4 amperes per centimeter of channel width and an N-channel saturation current of at least 7 amperes per centimeter of channel width, with a leakage current of less than 10 picoamperes per micron of channel length using power supplies of between 0 and 5 volts.

Fermi threshold field effect transistor including doping gradient regions

A high saturation current, low leakage, Fermi threshold field effect transistor includes a predetermined minimum doping concentration of the source and drain facing the channel to maximize the saturation current of the transistor. Source and drain doping gradient regions between the source/drain and the channel, respectively, of thickness greater than 300 .ANG. are also provided. The threshold voltage of the Fermi-FET may also be lowered from twice the Fermi potential of the substrate, while still maintaining zero static electric field in the channel perpendicular to the substrate, by increasing the doping concentration of the channel from that which produces a threshold voltage of twice the Fermi potential. By maintaining a predetermined channel depth, preferably about 600 .ANG., the saturation current and threshold voltage may be independently varied by increasing the source/drain doping concentration facing the channel and by increasing the excess carrier concentration in the channel, respectively. A Fermi-FET having a gate insulator thickness of less than 120 .ANG., and a channel length of less than about 1 .mu.m can thereby provide a P-channel saturation current of at least 4 amperes per centimeter of channel width and an N-channel saturation current of at least 7 amperes per centimeter of channel width, with a leakage current of less than 10 picoamperes per micron of channel length using power supplies of between 0 and 5 volts.

High saturation current, low leakage current fermi threshold field

A field effect transistor includes a polycrystalline silicon gate having a semiconductor junction therein. The semiconductor junction is formed of first and second oppositely doped polycrystalline silicon layers, and extends parallel to the substrate face. The polycrystalline silicon gate including the semiconductor junction therein is perfectly formed by implanting ions into the top of the polycrystalline silicon gate simultaneous with implantation of the source and drain regions. The semiconductor junction thus formed does not adversely impact the performance of the field effect transistor, and provides a low resistance ohmic gate contact. The gate need not be masked during source and drain implant, resulting in simplified fabrication.

Method of fabricating field effect transistor having polycrystalline

A random access memory (RAM) includes a plurality of sensing circuits. During a read operation, the RAM detects that one of the sensing circuits has sensed a binary digit. In response, the read operation is terminated and an idle operation is initiated to provide a self-timing RAM. During a write operation, the data which is stored in a RAM cell is also sensed by one of the sensing circuits and the memory detects that one of the sensing circuits has sensed the stored data. In response, the write operation is terminated and an idle operation is initiated. Self-timing read and write operations are thereby provided.

Self-timing random access memory

A differential latching inverter uses a pair of cross-coupled inverters having a skewed voltage transfer function to rapidly sense a differential signal on a pair of bit lines in a random access memory and provide high speed sensing during a read operation. The differential latching inverter may also include a and additional pull-up circuits to enhance high speed pair of symmetrical transfer function output inverters operation. The outputs of all of the differential latching inverters may be directly connected to a pair of OR gates with the output of one OR gate signifying that a logical ONE has been read and the output of the second OR gate signifying that a logical ZERO has been read. The differential latching inverter may be used in a memory architecture having primary bit lines and signal bit lines, with a differential latching inverter being connected to each pair of signal bit lines. The primary bit lines and signal bit lines are coupled to one another during read and write operations and decoupled from one another otherwise. The read and write operations may be internally timed without the need for external clock pulses in response to a high speed address change detection system, and internal timing signals generated by delay ring segment buffers. A high speed, low power random access memory may thereby be provided.

Random access memory including or gate sensing networks

A differential latching inverter uses a pair of cross-coupled inverters having a skewed voltage transfer function to rapidly sense a differential signal on a pair of bit lines in a random access memory and provide high speed sensing during a read operation. The differential latching inverter may also include a pair of symmetrical transfer function output inverters and additional pull-up circuits to enhance high speed operation. The differential latching inverter may be used in a memory architecture having primary bit lines and signal bit lines, with a differential latching inverter being connected to each pair of signal bit lines. The primary bit lines and signal bit lines are coupled to one another during read and write operations and decoupled from one another otherwise. The read and write operations may be internally timed without the need for external clock pulses in response to a high speed address change detection system, and internal timing signals generated by delay ring segment buffers. A high speed, low power random access memory may thereby be provided.

Read and write timing system for random access memory

The pass transistors in a random access memory array are activated only upon coincident (simultaneous) selection of both the associated row and the associated column of the memory cell; otherwise, activation of the pass transistors is prevented. Thus, when a word line is selected, only the pass transistors in the memory cell corresponding to a simultaneously selected bit line is active, rather than all of the pass transistors pairs connected to the word line. Transient power consumption during word line selection and deselection is thereby reduced. Coincident pass transistor activation may be obtained by providing a column select line for each column of the memory array, and gating means in each cell which electrically activates the associated pass transistors only upon simultaneous selection of the associated column select line and the associated word line, and for preventing activation of the associated pass transistors otherwise. When the column select lines and gating means are used, shared bit lines may be provided in the array. A single shared bit line may be used between adjacent columns of cells since only one of the columns will be selected by the column select line. A high density memory design is therefore provided.

Coincident activation of pass transistors in a random access memory

A high current Fermi-FET includes an injector region of the same conductivity type as the Fermi-Tub region and the source and drain regions, located adjacent the source region and facing the drain region. The injector region is preferably doped at a doping level which is intermediate the relatively low doping concentration of the Fermi-Tub and the relatively high doping concentration of the source region. The injector region controls the depth of the carriers injected into the channel and maximizes injection of carriers into the channel at a predetermined depth below the gate. The injector region may also extend to the Fermi-tub depth to decrease bottom leakage current. Alternatively, a bottom leakage current control region may be used to decrease bottom leakage current. Lower pinch-off voltage and increased saturation current are obtained by providing a gate sidewall spacer which extends from adjacent the source injector region to adjacent the sidewall of the polysilicon gate electrode of the Fermi-FET. The gate sidewall spacer preferably comprises an insulator having permittivity which is greater than the permittivity of the gate insulating layer.

High current fermi threshold field effect transistor

Field effect transistor having polycrystalline silicon gate junction

An improved Fermi FET structure with low gate and diffusion capacity allows conduction carriers to flow within the channel at a predetermined depth in the substrate below the gate, without requiring an inversion layer to be created at the surface of the semiconductor. The low capacity Fermi FET is preferably implemented using a Fermi Tub having a predetermined depth, and with a conductivity type opposite the substrate conductivity type and the same conductivity type as the drain and source diffusions.

Fermi threshold field effect transistor with reduced gate and diffusion

A Fermi-FET includes a Fermi-tub region at a semiconductor substrate surface, wherein the Fermi-tub depth is bounded between a maximum tub depth and a minimum tub depth. The Fermi-tub depth is sufficiently deep to completely deplete the Fermi-tub region by the substrate tub junction at the threshold voltage of the field effect transistor, and is also sufficiently shallow to produce a closed inversion injection barrier between the source region and the drain region below the threshold voltage of the Fermi-FET. High saturation current and low leakage current are thereby produced simultaneously. Source and drain injector regions and a gate sidewall spacer may also be provided.

Bounded tub fermi threshold field effect transistor

A differential latching inverter uses a pair of cross-coupled inverters having a skewed voltage transfer function to rapidly sense a differential signal on a pair of bit lines in a random access memory and provide high speed sensing during a read operation. The differential latching inverter may also include a pair of symmetrical transfer function output inverters and additional pull-up circuits to enhance high speed operation. The differential latching inverter may be used in a memory architecture having primary bit lines and signal bit lines, with a differential latching inverter being connected to each pair of signal bit lines. The primary bit lines and signal bit lines are coupled to one another during read and write operations and decoupled from one another otherwise. The read and write operations may De internally timed without the need for external clock pulses in response to a high speed address change detection system, and internal timing signals generated by delay ring segment buffers. A high speed, low power random access memory may thereby be provided.

Random access memory architecture including primary and signal bit lines

A data input register for a random access memory includes a data input line which is coupled to TRUE and COMPLEMENT outputs. A first and a second Ring Segment Buffer is connected to a respective one of the TRUE and COMPLEMENT outputs. The Ring Segment Buffer produces TRUE and COMPLEMENT binary signals at relatively fast rise time compared to the relatively slow rise time binary input signal. The Ring Segment Buffer outputs are coupled to a write control circuit for writing data into a selected memory cell of a random access memory array. The data input circuit architecture can also be used to produce relatively fast rise time TRUE and COMPLEMENT binary signals from a relatively slow rise time binary input signal for other applications.

Data input register for random access memory

An address change detection system detects a change in an address input in a memory to initiate a read or write operation. The address change detection system uses a transition detection delay unit for each address bit of the memory. The transition detection delay unit is responsive to a change in an associated address bit to provide a clock output pulse of predetermined duration. The transition detection delay unit comprises a latch which is coupled to the associated address bit, and a pair of Delay Ring Segment Buffers, each coupled to a respective output of the latch. The output of the Delay Ring Segment Buffer is provided to cascaded NAND gates to form the output of the transition detection delay unit. The outputs of all of the transition detection delay units are provided to an OR gate, the output of which provides an indication of an address change. The address change detection circuit can also be used to detect a change in at least one of a plurality of binary valued inputs for applications other than memory systems.

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Albert W Vinal