Nxp B.v.

Albert W Marsman

Nicolaas Lambert

Pierre Hermanus Woerlee

Teunis Jan Ikkink

Victor M G Van Acht

Victor Van Acht

Teunis Jian Ikkink

Teunis J Ikkink

A memory matrix () comprises rows and columns of cells, each cell comprising a resistance hysteresis element () and a threshold element () coupled in series between a row terminal and a column terminal of the cell (). The resistance hysteresis element () has a mutually larger and smaller hysteresis thresholds of mutually opposite polarity respectively. Voltage differences are applied between the column terminals and the row terminals of cells () in a selected row, so as to perform read actions. These voltage differences have a read polarity so that the voltage across the cell () is in a direction corresponding to the larger hysteresis threshold. Voltage differences are applied between the column terminals and the row terminals of cells () in a selected row, so as to perform erase actions, all cells () of a selected row being erased collectively in the erase action. The voltage differences for erase actions have the read polarity. Furthermore voltage differences are applied between the column terminals and the row terminals of cells () in a selected row, so as to perform write actions. The voltage differences for the write actions have a write polarity corresponding to the smaller hysteresis threshold, for updating cells () that are selected dependent on write data.

Driving a memory matrix of resistance hysteresis elements

A control circuit () for a memory matrix is used that defines a write process that uses circuit state transitions between at least two idle circuit states, an all column update circuit state and a column selective update state. In the second. During access the control circuit switches back and forth to the column selective update state (W) from the first idle state (II) during execution of a column selective update command and back and forth to the all-column update state (E) from the second idle state () during execution of an all column update command. The control circuit () is retained in the first and second idle state (II,), without switching to the second and first idle state (, II) between execution of successive column selective update commands and all column update commands respectively.

Control of a memory matrix with resistance hysteresis elements

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Valkenswaard, Netherlands

Albert W Marsman