Winbond Electronics Corporation

Windbond Electronics Corp.

Winbond Electronics Corporation America

Albert T Wu

Dah-Bin Kao

Tung-Yi Chan

Loc Bao Hoang

A semiconductor memory array and methods therefor is provided herein comprising a substrate; a plurality of memory cell field effect transistors formed on said substrate and being arranged thereon into rows and columns of transistors, each transistor includes a channel region interposed between drain and source regions, and overlaid by a control gate region; a plurality of first diffused elongated regions formed within said substrate that electrically connect in common the drain regions of transistors in respective columns; a plurality of second diffused elongated region formed within said substrate that electrically connect in common the source regions of transistors in respective columns; and a plurality of elongated conductive line formed over said substrate that electrically connect in common the control gate regions of transistors in respective rows.

Semiconductor memory array with buried drain lines and processing methods therefor

A method is disclosed for creating a sub-minimum opening in a semiconductor device, comprising the steps of: a) providing a first layer; b) providing a second layer over said first layer; c) providing a third layer over said second layer; d) providing a photoresist mask over said third layer; e) etching said third layer to form defined structures; f) depositing a fourth layer for forming spacers; g) etching said fourth layer to form said spacers; and h) etching said first layer to form an opening in said first layer. In etching the fourth layer to form the spacers, the third layer is generally etched away to form an opening to the first layer, and, in the following step, an opening (or feature) can be etched on the first layer. Generally speaking, the first and third layers can be of any material and should have similar etching rate; the second and fourth layers can be of any material and should have similar etching rate. However, the material for the first and third layers versus the material for the second and fourth layers should have highly dissimilar etching rates. Materials for these layers include and are not limited to polysilicon, oxide, nitride, and metal.

Method for forming minute openings in semiconductor devices

A semiconductor memory array and methods therefor is provided herein comprising a substrate; a plurality of memory cell field effect transistors formed on said substrate and being arranged thereon into rows and columns of transistors, each transistor includes a channel region interposed between drain and source regions, and overlaid by a control gate region; a plurality of first diffused elongated regions formed within said substrate that electrically connect in common the drain regions of transistors in respective columns; a plurality of second diffused elongated regions formed within said substrate that electrically connect in common the source regions of transistors in respective columns; and a plurality of elongated conductive line formed over said substrate that electrically connect in common the control gate regions of transistors in respective rows.

An analog memory device includes a memory cell transistor and a memory follower transistor that share a common floating gate. The drain of the memory cell transistor is coupled to a first voltage source. The control gate of the memory cell transistor is coupled to a second voltage source. A programming transistor is coupled between the source of the memory cell transistor and a reference voltage. A comparator receives a first input analog signal to be stored in the memory cell transistor and is coupled to the memory follower transistor to receive the signal held on the floating gate. The output of the comparator is coupled to the control gate of the programming transistor to selectively turn it on to store the analog signal in the memory cell transistor.

Growing community of inventors

Palo Alto, CA, United States of America

Albert T Wu