Tandem Computers Incorporated

Public Wireless, Inc.

Array Technology, LLC

Albert S Lui

Mark S Walker

William T Fuller

William A Brant

David C Stallmo

Tom Sidlauskas

Wing Ming Chan

Edward J Rhodes

Strikumar R Chandran

Harald W Sammer

Power supply and heat sink modules are suitable for use in sealed outdoor enclosures. Circuit elements in the power supply modules are connected to multiple heat sinks. The heat sinks are combined in heat sink modules. The heat sink modules provide high thermal conductivity while avoiding electromagnetic interference.

Systems and methods for heat extraction in a power supply

A system and method for ensuring the completion and integrity of data modification operations to a redundant array data storage system and for ensuring the integrity of redundancy values in such a system. The system combines four elements: reliable host processing provided by primary and secondary CPU's with check pointing of operations, so that the secondary CPU can complete initiation of a data modification operation if the primary CPU fails; block-buffering of Write data in a host CPU adapter before transmission of the data to a RAID array controller, so that failure of the host CPU after buffering completes does not interfere with completion of the data modification operation; reliable array processing provided by primary and secondary array controllers with check pointing of operations, so that the secondary array controller can complete a data modification operation if the primary array controller fails; and battery-backup for the power supply to the array controller and the storage units comprising the storage array, or, in the alternative, non-volatile memory in the array controller sufficient to store all data modification operation command information for data records that have not been successfully written to the storage units, for use in subsequent retries.

System and method for ensuring write data integrity in a redundant array

An apparatus and method for monitoring the environment of remote components attached to a host processor by means of a standard interface bus having a limited number of address ports. The invention includes a host adapter incorporating a standard bus repeater component and an environment monitoring component. The environment monitoring component has a standard bus interface and is selectably coupled to the standard interface bus, and hence to a host processor. The host interface transceiver is coupled by means of a standard bus to the host processor, and is also selectably coupled to a drive interface transceiver by means of the standard bus. The drive interface transceiver is coupled by the standard bus to one or more storage devices. The host adapter is selectably switchable between two modes, such that either the drive interface transceiver is coupled through the host interface transceiver to the host processor, or the environment monitoring component is coupled to the host processor. The inventive system reduces the overhead of an environment monitoring system in terms of address ports on a standard bus having a limited number of address ports. In addition, the bus repeater component of the inventive system permits doubling the cable length limit imposed on certain standard buses, thereby permitting more remote location of one or more storage devices from a host processor.

Environment monitoring system for standard interface bus computer systems

A fault tolerant power supply system for providing reliable power to a redundant array of data storage units. The system includes one power supply module for each channel of the array of data storage units. A power supply failure will not impact the ability of the data storage system to recover data due to the ability of the data storage system to reconstruct data in an unavailable channel from the data storage units of each other channel. The use of independent power supplies provides a power supply system which has a power capability equal to the sum of the power requirements of the data storage units, and voltage outputs just sufficient to meet the voltage requirements of the data storage units.

Fault tolerant power supply for an array of storage devices

A fault-tolerant storage device array using a copyback cache storage unit for temporary storage. When a Write occurs to the RAID system, the data is immediately written to the first available location in the copyback cache storage unit. Upon completion of the Write to the copyback cache storage unit, the host CPU is immediately informed that the Write was successful. Thereafter, further storage unit accesses by the CPU can continue without waiting for an error-correction block update for the data just written. In a first embodiment of the invention, during idle time for relevant storage units of the storage system, an error-correction block is computed for each 'pending' data block on the copyback cache storage unit, and the data block and corresponding error-correction block are copied to their proper location in the RAID system. The copyback cache storage unit in effect stores 'peak load' Write data and then completes the actual Write operations to the RAID system during relatively quiescent periods of I/O accesses by the CPU. In a second embodiment of the invention, after Write data is logged to the copyback cache storage unit, normal Read-Modify-Write operation by the RAID system controller continues in overlapped fashion with other CPU I/O accesses using Write data in the controller's buffer memory. Performance is enhanced because the CPU can continue processing as soon as the simple Write operation to the copyback cache storage unit completes, thus eliminating the delay caused by a normal Read-Modify-Wrote RAID system. In this embodiment, the copyback cache storage unit acts more as a running 'log' of Write data.

Storage device array architecture with copyback cache

A multiprocessing computer system with data storage array systems allowing for linear and orthogonal expansion of data storage capacity and bandwidth by means of a switching network coupled between the data storage array systems and the multiple processors. The switching network provides the ability for any CPU to be directly coupled to any data storage array. By using the switching network to couple multiple CPU's to multiple data storage array systems, the computer system can be configured to optimally match the I/O bandwidth of the data storage array systems to the I/O performance of the CPU's.

Linear and orthogonal expansion of array storage in multiprocessor

The present invention is an input/output controller for providing total data integrity for any single point failure. The I/O controller comprises a processor module having two microprocessors, an associated memory, a direct memory access module ('DMA'), and a processor support module ('PSM'); a device drive interface; and a channel interface. The two microprocessors are operated in lockstep as a dual modular redundant processor system. The processors provide true and complement, respectively, addresses, data and control strobes. The PSM compares the true and complement data to detect errors (i.e., corresponding data bits not being a true-complement pair) and generates parity protected data (and checks parity) on the data bus. The PSM also generates and checks dual railed control strobes and provides synchronization of all control strobes and interrupt signals to enable the tru-complement pair of microprocessors to operate in lockstep. The DMA compares the redundant addresses from the processors to detect errors and to generate parity protected addresses (and check parity) on the address bus. The DMA also generates the checks bus arbitration signals and controls direct memory access. Self-checking checkers are used to check the various dual railed, true-complement pairs of signals to detect, locate and isolate internal faults. Mis-compares between true-complement address, data and control signals and parity errors detected in reading program instructions from memory all are treated as fatal errors, which cause both processors to halt. Other types of errors are treated as nonfatal, which cause processor exceptions during which appropriate programming is executed to locate and isolate such errors.

Growing community of inventors

San Jose, CA, United States of America

Albert S Lui