Intel Corporation

Albert Rudy Nelson

Gary A Solomon

Karl H Mauritz

Aniruddha Kundu

Hany M Fahmy

David W Frame

Jerzy B Kolinski

Peter A Ward

Taha Mughir

Christopher J Banyai

Tom Rampone

Sami Khouli

Quing-Lun Chen

Joseph Manaloor

Irfan Syed

Briefly, in accordance with one embodiment of the invention, a system includes two boards coupled by a bus. The bus having a dual-terminated transmission line that communicatively couples a memory control hub with a memory repeater hub that each have a Rambus ASIC Cell (RAC). Briefly, in accordance with another embodiment of the invention, a connector has two metal traces that are of different lengths. The parasitic capacitance of the longer metal trace is increased so that the impedance of the two metal traces is substantially equal.

Apparatus and method for coupling to a memory module

A method and apparatus for low pin count firmware hub recovery on a circuit board having a firmware hub includes coupling a firmware hub recovery module having a firmware program onto the circuit board, establishing communication between a central processing unit (CPU) and the firmware hub recovery module, and reprogramming the firmware hub by the firmware program.

Low pin count (LPC) firmware hub recovery

A method and apparatus for programming firmware on a circuit board without powering the entire circuit board includes a firmware interface which can be isolated from the rest of the circuit board and a logic module for programming the firmware. The firmware interface includes a connector which supports powering the circuit board as well as permitting programming from the logic module.

Firmware field programming interface and module for programming non-volatile memory on a circuit board while isolating the processor from power using expansion bus controller

Flexible control of access to a Basic Input/Output System memory is provided by a programmable non-volatile storage unit that stores a non-volatile signal and generates a control signal based on the non-volatile signal. A control circuit coupled to the programmable non-volatile storage unit receives the control signal from the non-volatile storage unit. The control circuit also receives a BIOS memory address signal and generates a modified BIOS memory address signal. In this way, different BIOS programs may be accessed on boot-up.

Flexible control of access to basic input/output system memory

An improved power management system provides a dual mode power supply that supplies normal voltages and standby voltages. When the computer is placed in a power saving mode, the power supply is controlled to cease supplying the normal voltages to conserve power. While the computer is in the power saving mode, the standby power is supplied to specific devices that may be involved in waking the computer. When an I/O device or another device detects computer activity while in the power saving mode, a wake signal is generated and input to a power management device. The power management device then controls the power supply to supply the normal voltages to wake the computer.

Supplying standby voltage to memory and wakeup circuitry to wake a computer from a low power mode

A computer includes a dual mode power supply that includes a main voltage converter and a standby voltage converter. The main voltage converter generates a main operating voltage at a normal operating current. The standby voltage generator generates a standby voltage at a standby current. The power supply outputs a dual mode output that includes both the main voltage and the standby voltage. The standby current is less than the normal operating current. The computer includes a host processor, a memory array, and a wake-up device. A power management device is coupled to the host processor and receives at least the standby voltage. The dual mode output from the power supply is input to the wake-up device and the memory array to allow the computer to be placed in a power saving mode by terminating supply of the main voltage. While in the power saving mode and receiving only the standby voltage, the wake-up device can wake-up the computer.

Computer having a dual mode power supply for implementing a power saving

A flexible non-volatile memory controller that provides external boot block protection and provides support for non-volatile memory devices having different sizes is disclosed. The flexible non-volatile memory controller includes a boot block protection unit that provides external boot block protection for a non-volatile memory device without internal boot block protection. The boot block protection unit prevents external devices from writing to a prespecified block of memory in the non-volatile memory device in a normal mode. The flexible non-volatile memory controller also includes a memory expansion unit that is adapted to control non-volatile memory devices having different sizes.

Flexible non-volatile memory controller with boot block emulation

The reset circuit including a logic gate coupled to an electrical component containing the CMOS memory. The logic gate includes an output and at least a first and second inputs. The first input is configured to receive a first signal indicating that a power-down sequence has been requested. The second input, however, is configured to receive a second signal being a system reset signal. As a result, during a power-down sequence, CMOS memory is precluded from being accessed almost immediately after the first signal has been deactivated while other devices are powered-down in a normal fashion.

Circuit and method for using early reset to prevent CMOS corruption with

An interrupt handling mechanism for converting PCI agent interrupts into interrupts compliant with a secondary bus standard interrupt protocol. PCI agent interrupts are processed by programmable logic for converting PCI compliant interrupts into, for example, ISA bus standard compliant interrupts for processing by a computer system which implements both a PCI bus and ISA bus. A programmable register provides for selecting which ISA interrupt will be generated by the programmable logic in response to a PCI agent interrupt.

PCI to ISA interrupt protocol converter and selection mechanism

An interconnect mechanism for allowing use of an IDE compatible add-in card in a PCI compliant expansion slot. Unused PCI pins are exploited to provide for proper routing of necessary interrupt signals from an IDE add-in card. The presence of the IDE card in the PCI slot enables signaling circuitry for routing IDE interrupts to the computer system's interrupt controller and reroutes existing hard disk interrupt signals to the interrupt controller as a secondary hard disk interrupt. Another otherwise unused pin is exploited to provide a signal for lighting the computer system's hard disk active indicating LED. The gating circuitry is provided such that non-IDE, PCI-compliant add-in cards are provided with unaffected operation in the PCI slot.

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Olympia, WA, United States of America

Albert Rudy Nelson