Stretch, Inc.

Tensilica, Inc.

Synopsys, Inc.

Albert RenRui Wang

Scott David Johnson

Gareld Howard Banta

Jeffrey Mark Arnold

Ricardo E Gonzalez

Kenneth Mark Williams

Earl A Killian

Christopher Rowen

Robert P Wilson

Christopher Mark Songer

Abhijit Ghosh

John Newlin

Richard L Rudell

Richard Rudell

Bruce Saylors McNamara

Bernard Rosenthal

A source processing node communicates with a destination processing node though a channel that has bandwidth requirements and is uni-directional. The source processing node generates the channel to the destination processing node. The destination processing node then accepts the channel. The source processing node allocates a transmit buffer for the channel. The destination processing node also allocates a receive buffer for the channel. A source processing element writes data to the transmit buffer for the channel. A source network interface transmits the data from the transmit buffer of the source processing node over the channel. A destination network interface receives the data into the receive buffer for the channel. A destination processing element receives the data from the receive buffer.

Configuring a multi-processor system

An integrated circuit with selectable input/output includes a first processor configured to execute instructions, an input/output interface configured to receive and transmit standard input/output communications, an inter-processor interface configured to process interprocessor communications with a second processor, and selection circuitry coupled to both the input/output interface and the inter-processor interface and configured to select between the input/output interface and the inter-processor interface.

Systems and methods for selecting input/output configuration in an integrated circuit

A processing system with reconfigurable instruction extensions includes a processor, programmable logic, a register file, and a load/store module. The processor executes a computer program comprising a set of computational instructions and at least one instruction extension. The programmable logic receives configuration information to configure the programmable logic for the instruction extension and executes the instruction extension. The register file is coupled to the programmable logic and stores data. The load/store module transfers the data directly between the register file and a system memory.

Programmable logic configuration for instruction extensions

A system for processing applications includes processor nodes and links interconnecting the processor nodes. Each node includes a processing element, a software extensible device, and a communication interface. The processing element executes at least one of the applications. The software extensible device provides additional instructions to a set of standard instructions for the processing element. The communication interface communicates with other processor nodes.

Systems and methods for software extensible multi-processing

A system and method provide unaligned load/store functionality for a processor that supports only aligned load/store instructions. An exemplary embodiment includes an extension adapter including registers for storing data and load/store buffers for realigning data. A processor executes aligned load/store instructions that transfer data in multiples of bytes. Instructions are included for transferring data between memory and the load/store buffers, initializing and transferring data, initializing and transferring data in numbers of bits, advancing or offsetting a data pointer, and for flushing the load/store buffers. In a preferred embodiment, the extension adapter comprises a wide register file for buffering full words of data, load/store buffers formed from multiple single-bit registers for buffering data bits and streaming data for use by the processor, and address generators for pointing to data or memory addresses.

Instruction set for efficient bit stream and byte stream I/O

A method is provided for modifying a program written in a standard programming language so that when the program is compiled both an executable file is produced and an instruction is programmed into a programmable logic device of a processor system. The method includes identifying a critical code segment of a program, rewriting the critical code segment as a function, revising the program, and compiling the program. Revising the program includes designating the function as code to be compiled by an extension compiler and replacing the critical code segment of the program with a statement that calls the function. Compiling the program includes compiling the code with an extension compiler to produce a header file and the instruction for the programmable logic device. Compiling the program also includes using a standard compiler to compile the remainder of the program together with the header file to generate the executable file.

Defining instruction extensions in a standard programming language

A system for adding advanced instructions to a microprocessor includes a language for formally capturing the new instructions and a method for generating hardware implementations and software tools for the extended processors. The extension language provides for additions of VLIW instructions, complex load/store instructions, more powerful description styles using functions, more powerful register operands, and a new set of built-in modules. The method is capable of generating fully-pipelined micro-architectural implementations for the new instructions in the form of synthesizable HDL descriptions which can be processed by standard CAD tools. The method is also capable of generating software components for extending software development tools for the microprocessor with new instructions.

Method and apparatus for adding advanced instructions in an extensible processor architecture

A video processing system with reconfigurable instructions includes a processor, a first register file in the processor, an extension adapter, programmable logic, a second register file coupled to the programmable logic, and a load/store module. The processor executes a video application that contains an instruction extension not native to the instruction set of the processor. The extension adapter detects the instruction extension in the video application. The programmable logic device is configured to execute the instruction extension. The programmable logic device then executes the instruction extension. The load/store module transfers data between the first register file and the second register file, and transfers data directly between the second register file and a system memory for use by the processor in processing the video application.

Video processing system with reconfigurable instructions

A new general method for building hybrid processors achieves higher performance in applications by allowing more powerful, tightly-coupled instruction set extensions to be implemented in reconfigurable logic. New instructions set configurations can be discovered and designed by automatic and semi-automatic methods. Improved reconfigurable execution units support deep pipelining, addition of additional registers and register files, compound instructions with many source and destination registers and wide data paths. New interface methods allow lower latency, higher bandwidth connections between hybrid processors and other logic.

High-performance hybrid processor with configurable execution units

A debugging system and debugging techniques for configurable processors remove the requirement of foreknowledge of specific configurable processor information from components of the debugging system where obtaining that foreknowledge is costly. The system is part of an environment that generates a processor where the proper information is generated in the right forms for such use.

Debugging apparatus and method for systems of configurable processors

A system and method for adding reconfigurable computational instructions to a reduced instruction set computer. A computer program contains instruction extensions not native to the instruction set of the processor core and is loaded into an instruction memory accessible by the processor core of the computer. The computer program is then detected for containing the instruction extension. The programmable logic device is then configured to execute the instruction extension. The programmable logic device then executes the instruction extension for use by the processor core in processing the computer program.

Reconfigurable instruction set computing

A universal synchronization element is used in a static timing verification system to represent selected combinational primitive elements, synchronous primitive elements and external primitive elements in the user's synchronous digital circuit. Each of these digital circuit element in a user's digital circuit design is represented by a corresponding universal synchronization element having a propagation time characteristic equivalent to the digital circuit element and a stable time characteristic equivalent to the digital circuit element. The propagation and stable time characteristics are defined in relation to a clock signal for the digital circuit element in the user's circuit that the universal synchronization element represents. The universal synchronization element does not a fixed timing relationship between the signals on its input and output terminals. The adjustment of stable interval starting and end times and the propagation interval starting and end times is sufficient to represent the timing characteristics of circuit element with the universal synchronization element of this invention.

Method and structure for use in static timing verification of

A new method and structure are provided for simulating the time delay associated with signal propagation through a mapped and optimized logic network for a selected target technology using only information from an unmapped logic network. For each target technology, the method and structure include the time delay characteristics of the mapping and optimization strategies used to generate an optimized network using the library of standard gates for that target technology. The functional complexity of each unmapped logic node and the complexity of the fanout for each unmapped logic node are also included in the simulated time delay.

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Los Altos, CA, United States of America

Albert RenRui Wang