Altera Corporation

Albert Ratnakumar

Qi Xiang

Jun Liu

Jeffrey Xiaoqi Tung

Irfan Rahim

Andy Louie Lee

Jeffrey T Watt

Yanzhong Xu

Srinivas Perisetty

Shankar Sinha

Shih-Lin S Lee

Wilson Wong

Weiqi Ding

Shuxian Chen

Cheng-Hsiung Huang

Simardeep Maangat

Mark Chan

Yow-Juang Bill Liu

Shuang Xie

Peter Smeys

Peter John McElheny

Yan Cui

William Bradley Vest

Lu Zhou

Bradley Jensen

Charu Sardana

Yanzhong Yu

Apparatus for integrated capacitors and associated methods are disclosed. In one embodiment, an integrated capacitor includes a first plurality of metal members that are fabricated using a first plurality of metal layers, and are oriented in a first orientation. The integrated capacitor also includes a second plurality of metal members that are fabricated using a second plurality of metal layers. The second plurality of metal members are oriented transverse to the first orientation. The integrated capacitor further includes a third plurality of metal members, which are fabricated using a third plurality of metal layers, and are oriented in the first orientation.

Apparatus and associated methods for capacitors with improved density and matching

Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.

Integrated circuits with asymmetric and stacked transistors

Integrated circuits with bipolar transistors are provided. In one embodiment, a bipolar transistor may include an emitter region, a first base region that surrounds the emitter region, a collector region that surrounds the first base region, and a second base region that surrounds the collector region. Respective well taps may be formed within the emitter, collector, and the second base regions. A deep doped well having the same doping type as the base regions may extend beneath the emitter, collector, and base regions. In another embodiment, the bipolar transistor may include an emitter region, a base region that surrounds the emitter region, and a collector region that surrounds the base region. Respective well taps may be formed within the emitter, base, and collector regions. A deep doped well having the same doping type as the base region may extend beneath the emitter and only a portion of the base region.

Methods for fabricating PNP bipolar junction transistors

A programmable device with a metal oxide semiconductor field effect transistor (MOSFET) surrounded by a programmable substrate region is described. The MOSFET has a source and drain region separated by a channel region with an insulating region and gate disposed above the channel region. A junction disposed within the substrate region controls the programmable substrate region. Biasing the junction depletes the substrate region, which isolates the body of the MOSFET from a secondary well. When the junction is left unbiased, the body of the MOSFET is electrically coupled to the secondary well.

Programmable device with a metal oxide semiconductor field effect transistor

Metal-oxide-semiconductor transistors are provided. A metal-oxide-semiconductor transistor may be formed on a semiconductor substrate. Source and drain regions may be formed in the substrate. A gate insulator such as a high-K dielectric may be formed between the source and drain regions. A gate may be formed from multiple gate conductors. The gate conductors may be metals with different workfunctions. A first of the gate conductors may form a pair of edge gate conductors that are adjacent to dielectric spacers. An opening between the edge gate conductors may be filled with the second gate conductor to form a center gate conductor. A self-aligned gate formation process may be used in fabricating the metal-oxide-semiconductor transistor.

Method of fabricating integrated circuit transistors with multipart gate conductors

A method that includes using a PMOS pass gate to couple a first line to a second line, where a gate terminal of the PMOS pass gate is coupled to an output terminal of a memory cell, is described. In one implementation, the PMOS pass gate has a negative threshold voltage. In one implementation, the first line and the second line are respectively first and second interconnect lines of an IC.

Method of using a PMOS pass gate

A first trimming capacitor having a first terminal and a second terminal is coupled in parallel between a first terminal and a second terminal of a first capacitor. The first trimming capacitor comprises a first plurality of switched capacitors having different capacitances coupled in parallel. Each of the switched capacitors comprises a switch capacitor and a switch coupled in series. In an illustrative application the first capacitor and the first trimming capacitor are coupled between an output terminal of an operational amplifier (op-amp) and an inverting input terminal of the op-amp. A second capacitor and a second trimming capacitor similar to the first capacitor and the first trimming capacitor are coupled between an input and the inverting input terminal of the op-amp.

High resolution capacitor

Asymmetric transistors such as asymmetric pass transistors may be formed on an integrated circuit. The asymmetric transistors may have gate structures. Symmetric pocket implants may be formed in source-drains on opposing sides of each transistor gate structure. Selective heating may be used to asymmetrically diffuse the implants. Selective heating may be implemented by patterning the gate structures on a semiconductor substrate so that the spacing between adjacent gate structures varies. A given gate structure may be located between first and second adjacent gate structures spaced at different respective distances from the given gate structure. A larger gate structure spacing leads to a greater substrate temperature rise than a smaller gate structure spacing. The pocket implant diffuses more in portions of the substrate with the greater temperature rise, producing asymmetric transistors. Asymmetric pass transistors may be controlled by static control signals from memory elements to implement circuits such as programmable multiplexers.

Integrated circuits with asymmetric pass transistors

Integrated circuits that include resistors are provided. An integrated circuit resistor may include a conductive structure disposed over a semiconductor substrate. An oxide layer may be interposed between the conductive structure and a top surface of the semiconductor substrate. A shallow trench isolation structure may be formed in the substrate directly beneath the oxide layer. The shallow trench isolation structure may be formed in a given region in the substrate that is contained within a surrounding n-well and a deep n-well. The given region within which the shallow trench isolation structure is formed may exhibit native substrate dopant concentration levels; the given region is neither an n-well nor a p-well. The surrounding n-well and the deep n-well may be reversed biased to help fully deplete the given region so that parasitic capacitance levels associated with the resistor are minimized.

Integrated circuit resistors with reduced parasitic capacitance

An IC that includes a memory cell and a pass gate coupled to the memory cell, where the pass gate includes a PMOS transistor, is described. In one implementation, the PMOS transistor has a negative threshold voltage. In one implementation, the memory cell includes thick oxide transistors.

PMOS pass gate

Integrated circuit transistors with multipart gate conductors

Integrated circuits may be provided that include memory elements that produce output control signals and corresponding programmable logic circuitry that receives the output control signals from the memory elements. The memory elements may include bistable storage elements formed from circuits such as cross-coupled inverters. The inverters may include n-channel metal-oxide-semiconductor transistors with p-metal gate conductors and n-channel metal-oxide-semiconductor transistors with p-metal gate conductors. These gate conductor assignments are the reverse of the gate conductor assignments used in the n-channel and p-channel transistors in other circuitry such as the programmable logic circuitry. The reversed gate conductor assignments increase the threshold voltages of the transistors in the memory elements to improve reliability in scenarios in which the memory elements are overdriving pass transistors in the programmable logic circuitry.

Memory element transistors with reversed-workfunction gate conductors

Nonvolatile memory element circuitry is provided that is based on metal-oxide-semiconductor transistor structures. A nonvolatile memory element may be based on a metal-oxide-semiconductor transistor structure that has a gate, a drain, a source, and a body. During programming operations, control circuitry floats the body while applying a positive voltage to the drain and a negative voltage to the source. This causes the drain and source, which serve as the collector and emitter in a parasitic bipolar transistor, to break down. The drain-to-source (collector-to-emitter) breakdown causes sufficient current to flow through the source to alter the source electrode and thereby increase the resistance of the source significantly. During sensing operations, control circuitry may apply a voltage across the drain and source while grounding the body to determine whether the memory element has been programmed.

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San Jose, CA, United States of America

Albert Ratnakumar