Other

Sharp Kabushiki Kaisha Corporation

Albert O Adan

Shunpei Yamazaki

Jun Koyama

Masaya Isobe

The PLL circuit of the present invention includes a voltage-controlled oscillator, a loop filter, and a charge pump which controls a voltage of the loop filter while the voltage-controlled oscillator is not oscillating. Therefore, it is possible, even while the voltage-controlled oscillator is not oscillating, to control a voltage for the charge pump so that it is equal to a voltage when the voltage-controlled oscillator is oscillating at a predetermined frequency. Accordingly, by the loop filter outputting a voltage signal to the voltage-controlled oscillator when the PLL circuit is turned on, the pull-in time can be shortened.

PLL circuit having reduced pull-in time

An SRAM cell comprising, at least, two driving transistors and two transfer transistors, and two load transistors each comprised of a TFT and disposed on these transistors through a layer insulation film, the load transistors having an active region comprising an Si film having improved crystallizability of amorphous Si by the solid phase growth technique using a catalytic element, and a barrier layer for preventing the catalytic element from diffusion into the driving transistors and the transfer transistors which is disposed between the layer insulation film and the load transistors.

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Ikoma, Japan

Albert O Adan