Fujitsu Corporation

Hal Computer Systems, Inc.

Albert Mu

Jeffrey D Larson

Thomas M Wicki

Raghu Sastry

Richard L Schober, Jr

John R Slice

Patrick James Helland

A switch system and method transfer a data packet from a source data port to one or more destination data ports through a switch. The system includes at least one crosspoint circuit. A crosspoint circuit in the switch system includes a first and a second reduced voltage swing line, a first and a second transistor circuit for each data input path and a sense amplifier for a data port. The first reduced voltage swing line is coupled to the first transistor circuit, the second reduced voltage swing line is coupled to the second transistor circuit and both reduced voltage swing lines are connected to the sense amplifier. A method for transferring data using a crosspoint circuit includes a charging first voltage line and a second voltage line to a predetermined voltage level, discharging the predetermined voltage level in the first voltage line, maintaining the predetermined voltage level in the second voltage line concurrently with the discharging step, receiving a high clock signal at a sense amplifier, and generating an output signal based on a differential voltage level at the arrival of the clock signal.

Crossbar switch and method with crosspoint circuit

A system and method for controlling data transmission between two network elements. A first port of a transmitting element is coupled to a second port of a receiving element. The second port includes buffers for temporarily storing received data until the data can be sent to another element. Included in the transmitting element are a received-currently-full register (RCFR), a sent-and-not-received register (SANRR), and a buffer-busy register (BBR). The transmitting element checks its BBR to determine if a buffer in the receiving element is available. The availability of buffers can be determined using a single priority protocol or a multiple priority protocol. If a buffer is available, the transmitting element transmits a data frame to the receiving element and sets the SANRR and the BBR to indicate that a frame has been sent (and that no acknowledgment has been received), that the selected buffer in the receiver is full, and that no additional data frames are to be sent to this buffer until the buffer is empty. When data is received by the receiving element, it is sent to an available buffer. When the data is received by the buffer, the receiving element sets a bit in a currently-full register (CFR) and a bit in a next-message-to-send register (NMTSR). A control signal is transmitted by the data receiving element on the same signal line as data that is being sent from the data receiving element to the data transmitting element. The data receiving element can multiplex the frames being sent in this direction with the control signal. When the transmitting element receives the control signal, it resets a bit associated with a buffer in the SANRR if the bit is set in the SANRR and if the associated bit in the NMTSR portion of the control signal is set.

System and method for controlling data transmission between network

A switch system and method transfer a data packet from a source data port to one or more destination data ports through a switch. The system comprises a source input buffer, a first and a second source input path, a first and a second output path and at least one crosspoint circuit. The source input buffer includes a first and a second data section. The first and the second data sections are coupled to the first and the second input paths respectively. The first and the second input paths couple through the crosspoint circuits at each intersection with the first and the second output paths. The method includes loading the data packets into data sections of an input buffer, transferring each data packet across an input path dedicated for each data section, transmitting each data packet over its input path, and switching the data from the input path to the output path based on a voltage differential. A crosspoint circuit in the switch system includes a first and a second reduced voltage swing line, a first and a second transistor circuit for each data input path and a sense amplifier for a data port. The first reduced voltage swing line is coupled to the first transistor circuit, the second reduced voltage swing line is coupled to the second transistor circuit and both reduced voltage swing lines are connected to the sense amplifier. The method of the unit comprises the steps of charging a first and a second reduced voltage swing line to a predetermined voltage, discharging the voltage from the first reduced voltage swing line, maintaining the voltage in the second voltage line, receiving a clock signal at the sense amplifier, and generating an output signal based on a voltage differential between the voltage lines.

Crossbar switch and method with reduced voltage swing and no internal

A method and apparatus for detecting and isolating an interconnect fault in a packet switched network generates a parity check error code for status messages which are used for flow control in a packet switched network. The packet switched network uses a reverse flow control method wherein status messages are sent locally between adjacent nodes. A receiving node uses status messages to inform an adjacent node of the availability of the input buffers located in the receiving node. Included in the status message is a parity check code that is sent sequentially with the status message using two phases of a clock. The parity check code is a one bit parity check for each bit of the status message. Faults on the local interconnect are detected at the receiving node by performing a one bit parity check on the received status message using the accompanying parity code. Because the status message and the parity check code are transmitted over the same physical bit connections, the one bit parity checks detects any 'stuck at' or 'open' faults in the link.

Interconnect fault detection and localization method and apparatus

Arbitration apparatus and method coordinate access to an output of a routing device in a packet switching network. Access to the output is granted to requests having the highest priority in a current arbitration cycle. For requests having the same priority, access is granted to the first of such requests received. Before granting a request, the arbitration apparatus ensures a receiving input buffer has sufficient space for a data packet, as well as any higher priority traffic.

Method and apparatus for coordinating access to an output of a routing

An plesioasynchronous and asynchronous router circuit communicates with neighboring router circuits and nodes. Each of the router circuits includes a plurality of input ports for receiving frames of data and a plurality of output ports for transmitting frames of data. Each router circuit further includes a plurality of input buffers for storing frames of data received at an input port, and an arbiter system for choosing one of several input buffers associated with a particular one of said output ports. The arbiter system includes a plurality of arbiter subsystems associated with corresponding ones of said plurality of output ports. The plesioasynchronous and asynchronous router circuit further includes a crossbar switch for connecting an arbiter selected input buffer with a particular one of said output ports.

Low latency, high clock frequency plesioasynchronous packet-based

A differential sense amplifier includes positive feedback cross coupling to control operation in one mode as a differential sense amplifier and in another mode as a latch to control a data-latching load. Circuit nodes are precharged and equalized in response to applied enable signal.

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Milpitas, CA, United States of America

Albert Mu