Stmicroelectronics (rousset) Sas

Stmicroelectronics S.a.

Stmicroelectronics S.r.l.

Stmicroelectronics (grenoble 2) Sas

Albert Martinez

Jean Nicolai

William Orlando

Yannick Teglia

Michel Agoyan

Pascal Fornara

Patrick Haddad

Stéphan Courcambeck

Daniele Fronte

Stefano Lunghi

M William Orlando

The present disclosure relates to a circuit for testing a random number generator adapted to delivering a series of random bits and comprising at least one test unit configured to detect a defect in the series of random bits, said test circuit being adapted to verifying whether, after the detection of a first defect by the test unit, the number of random bits, generated by the random number generator without the detection of a second defect by said unit test, is smaller than a first threshold.

Random number generator

An electronic device includes: a non-volatile memory configured to store data including encrypted data; and a digital circuit. The digital circuit includes: a microprocessor configured to access the non-volatile memory and an internal memory; and a decryption circuit arranged on an interconnect network identifying an internal data path for exchanging the data between the non-volatile memory and the microprocessor, and connected to a memory controller of the non-volatile memory for receiving blocks of data from the non-volatile memory, the decryption circuit being configured to: perform a decryption on the fly of blocks of the data read from the non-volatile memory to obtain read decrypted data; generate first decryption masks corresponding to first blocks of data being read from the non-volatile memory at a given read address; and generate second decryption masks corresponding to second blocks of data to be read from the non-volatile memory at a next estimated read address.

Electronic device including a digital circuit for accessing encrypted data in a memory and corresponding method to access encrypted data in a memory

A circuit includes a random oscillation number generator (RONG) configured to generate first and second pulse signals at first and second RONG outputs. A first counter is coupled to the first RONG output and generates a first count at a first counter output. A second counter is coupled to the second RONG output and generates a second count at a second counter output. A selection circuit is coupled to the first and second counter outputs and to the first and second RONG outputs. A first pulse shaper is connected between the first RONG output and the first counter, and a second pulse shaper is connected between the second RONG output and the second counter.

Pulse counting circuit

A pulse counting circuit receives pulses supplied by a source circuit having at least two inverted pulse signal supply terminals. The circuit includes a first counter to count pulses of a first pulse signal and supply a first count and a second counter to count pulses of a second pulse signal and supply a second count. A selection circuit selects one of the first and second counts.

A delaying element includes a first XOR logic gate and a second XOR logic gate. A first input of the first XOR logic gate defines an input terminal. A first input of the second XOR logic gate is connected to an output of the first XOR logic gate. An output of the second XOR logic gate defines an output terminal. The second inputs of the first and second XOR logic gates are connected to a second input terminal.

Configurable delay line

A method for monitoring the execution of a program code by a monitoring program code may include storing instructions of the program code and instructions for monitoring the program code in the same program memory. Each instruction to be monitored and the associated monitoring instructions may be simultaneously extracted from the program memory, and the instruction to be monitored and the monitoring instructions may be executed.

Method and device for monitoring the execution of a program code

A logic two-to-one multiplexer includes: two input terminals; one output terminal; a control terminal. Four series-connected two-to-one multiplexers are connected such that a first multiplexer has its inputs connected to the input terminals, a last multiplexer has its output connected to the output terminal, and the other multiplexers have their respective inputs interconnected to the output of the previous multiplexer in the series association. Half of the multiplexers are controlled in reverse with respect to the other half of the multiplexers.

Multiplexer structure

A circuit generates a number of oscillations. The circuit includes a first branch with at least one delay line introducing symmetrical delays on rising edges and on falling edges and at least one asymmetrical delay element introducing different delays on rising edges and on falling edges. The circuit further includes a second branch looped back on the first branch and including at least one delay line introducing symmetrical delays on rising edges and on falling edges.

Generator of numbers of oscillations

A method for loading a program, contained in at least a first memory, into a second memory accessible by an execution unit, in which the program is in a cyphered form in the first memory, a circuit for controlling the access to the second memory is configured from program initialization data, instructions of the program, and at least initialization data being decyphered to be transferred into the second memory after configuration of the circuit.

Protection of memory areas

The present disclosure relates to a method for routing data between a sending unit and a receiving unit linked by a network in a processing system comprising several units, the method comprising steps of routing data in the network between the sending unit and the receiving unit, and of applying a process to the routed data, the process comprising several steps which are applied to the data by different units in the network receiving the data, to use latency times in data routing.

Data processing system having distributed processing means for using intrinsic latencies of the system

A thermally deformable assembly is formed in an integrated-circuit metallization level. The physical behavior of the metal forming the assembly brings the assembly into contact with a stop-forming body when subjected to a temperature change caused by a current flow. A natural rollback to the initial configuration in which the assembly is a certain distance away from the body is prevented. The state or configuration of the assembly is determined by a capacitive reader.

Electrically activatable integrated mechanical anti-rollback device with one or more positions

A circuit for controlling the access to at least one area of a memory accessible by a program execution unit, including a first instruction address input; at least one second data address input, the addresses coming from the execution unit; at least one function of correlation of these addresses; and at least one output of a bit for validating the fulfilling of conditions set by the correlation function.

Memory area protection circuit

A method for transmitting data between a first and a second point comprises the steps of transmitting data, from the first to the second point, together with a signature comprising bits of a first authentication code, and transmitting an acknowledgement, from the second to the first point. The length of the first authentication code is greater than the length of the signature and the first authentication code comprises hidden authentication bits. The acknowledgement is produced by using hidden authentication bits of a second authentication code presumed to be identical to the first, produced at the second point.

Data transmission method using an acknowledgement code comprising hidden authentication bits

A method for protecting the execution of a ciphering or deciphering algorithm against the introduction of a disturbance in a step implementing one or several first values obtained from second values supposed to be invariant and stored in a non-volatile memory in which, during an execution of the algorithm: a current signature of the first values is calculated; this current signature is combined with a reference signature previously stored in a non-volatile memory; and the result of this combination is taken into account at least in the step of the algorithm implementing said first values.

Growing community of inventors

Bouc Bel Air, France

Albert Martinez