International Business Machines Corporation

Globalfoundries Inc.

Infineon Technologies North America Corp.

Other

Siemens Aktiengesellschaft

Albert Manhee Chu

Brent A Anderson

Ruilong Xie

Junli Wang

Daryl Michael Seitzer

Lawrence Alfred Clevenger

Rohit Pradeep Shetty

John Atkinson Fifield

Ravikumar Ramachandran

Myung-Hee Na

Wagdi William Abadeer

Albert M Young

Thomas W Wyckoff

Carl John Radens

Dechao Guo

Frank David Ferraiolo

George Maria Braceras

Ronald A Piro

Jean-Marc Dortu

Reinaldo Ariel Vega

Kisik Choi

Nicholas Anthony Lanzillo

Jeffrey Scott Brown

Robert E Busch

Edward J Nowak

Robert J Gauthier, Jr

Julien Frougier

Michael Richard Ouellette

JunJun Li

Harold Pilo

Emre Alptekin

Kafai Lai

Jason D Hibbeler

Mujahid Muhammad

Kevin William Gorman

Robert J Allen

Daniel Nelson Maynard

Michael S Gray

Robert F Walker

Ezra D B Hall

Allan Robert Bertolet

William R Griffin

Mervyn Y Tan

Faye D Baker

Manikandan Viswanath

Ximeng Guan

Jonathan B Ashbrook

Eric Eastman

Effendi Leobandung

Veeraraghavan S Basker

Hemanth Jagannathan

Lars W Liebmann

Balasubramanian Pranatharthiharan

Terence B Hook

Daniel Mark Dreps

Heng Wu

Kevin Charles Gower

Huiming Bu

Robert C Wong

Joseph Andrew Iadanza

Rajasekhar Venigalla

Sean David Burns

John Christopher Arnold

Paul Christian Parries

Nazmul Habib

Ning Lu

Douglas Willard Stout

Christopher P Miller

David S Wolpert

Jason Eugene Stephens

Alexander Joel Suess

Tao Li

Somnath Ghosh

Daniel James Dechene

Kevin A Batson

Larry Wissel

Kai Zhao

Sagarika Mukesh

Paul T Gutwin

Alan C Thomas

Seong-Dong Kim

Roger Paul Gregor

Vikrant Kumar Chauhan

Eric Miller

Laura R Darden

Jason Edward Rotella

Eric D Johnson

Samuel K Weinstein

John G Petrovick, Jr

Jens Haetty

Teresa Thi Nguyen

Michael Sofranko

William J Rensch

Jane S Tu

Daryl M Seizter

Ezra Hall

Vidhi Zalani

Michael Bogaczyk

A semiconductor structure having improved performance is provided that includes a local enlarged via-to-backside power rail (VBPR) contact structure which connects a source/drain region of one field effect transistor (FET) to a backside power rail.

Local enlarged via-to-backside power rail

A microelectronic structure including a plurality of lower transistors and a plurality of upper transistor, where each of the plurality of lower transistors and the plurality of upper transistors includes a plurality of channel. Where an upper center vertical axis of each of the plurality of upper transistors is staggered from a lower center vertical axis of each of the lower transistors. A lower gate cut is located between each of the plurality of lower transistors. A first upper gate cut located adjacent to a first upper transistor of the plurality of upper transistors, where the first upper gate cut is in direct contact with a plurality of first channels of the first upper transistor.

Method and structure of forming independent contact for staggered CFET

A semiconductor memory cell comprising six vertical-transport field-effect transistors (VTFET) on a wafer. The six VTFET are in a first layer. The six VTFET are in a first row.

High density static random-access memory

Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a metal level, the metal level includes a metal strip including a notch at a side of the metal strip or a pass-through inside the metal strip, wherein the notch or the pass-through is at least partially filled with a dielectric material. The metal level further includes a conductive wiring that vertically passes through the metal strip. The conductive wiring is at least partially inside the notch or inside the pass-through and is insulated from the metal strip by the dielectric material. Methods of manufacturing the semiconductor structure are also provided.

Pass-through wiring in notched interconnect

A semiconductor device is provided. The semiconductor device includes a field effect transistor (FET) including first and second source/drain (S/D) epitaxial regions. The semiconductor device also includes a gate cut region at cell boundaries between the first and second S/D epitaxial regions, a dielectric liner and a dielectric core formed in the gate cut region, and a backside power rail (BPR) and a backside power distribution network (BSPDN). The semiconductor device also includes a power via passing through the dielectric core and connecting to the BPR and BSPDN, first metal contacts formed in contact with the first and second S/D epitaxial regions, and a via to backside power rail (VBPR) contact. The dielectric liner separates the power via from the first S/D epitaxial region.

Semiconductor device with power via

A VTFET is on a wafer and a backside power delivery network is on a backside of the wafer. A first backside contact is connected to a gate of the VTFET and a first portion of the backside power delivery network. The VTFET has a first width and the first width is a contacted poly pitch (CPP). The first backside contact may be at least the first width from the VTFET. The first backside contact may be double the first width from the VTFET.

Vertical-transport field-effect transistor with backside gate contact

Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a static random access memory (SRAM) cell. The SRAM cell may include a first section of the SRAM cell with a first pull-up transistor, first pull-down transistor, and first pass-gate transistor. The SRAM cell may include a second section of the SRAM cell with a second pull-up transistor, second pull-down transistor, and second pass-gate transistor. The first section of the SRAM cell and the second section of the SRAM cell may be arranged in a non-rectangular cell layout with the first pass-gate located at a first end of the non-rectangular cell layout and the second pass-gate at a second end of the non-rectangular cell layout opposite the first end.

High density stacked vertical transistor static random access memory structure

Embodiments of the invention include a first source region and a first drain region forming a first L-shaped layout. The first source and drain regions are formed on a bottom gate spacer material. Embodiments include a second source region and a second drain region forming a second L-shaped layout, the first L-shaped layout and the second L-shaped layout being interrupted by a gate. One of the first source and drain regions extends in a direction beyond the bottom gate spacer material to form the first L-shaped layout, wherein the direction is parallel to a lengthwise direction of the gate.

Stacked transistor layout for improved cell height scaling

A semiconductor structure includes a first field-effect transistor having a first back side source/drain contact, a second back side source/drain contact, and a first power line and a first signal line each connected to the first back side source/drain contact and the second back side source/drain contact, respectively. The semiconductor structure further includes a second field-effect transistor vertically stacked above the first field-effect transistor. The second field-effect transistor having a first front side source/drain contact, a second front side source/drain contact, and a first power line and a first signal line each connected to the first front side source/drain contact and the second front side source/drain contact, respectively.

Transistors with dual power and signal lines

A semiconductor structure including a first logic cell having a first plurality of nanosheet devices along an axis and a second logic cell having a second plurality of nanosheet devices along the axis. Nanosheets of the second plurality of nanosheet devices are wider than nanosheets of the first plurality of nanosheet devices. The first logic cell is a same type as the second logic cell. The first and second logic cells can include inverter circuits or NAND circuits or NOR circuits. When the first logic cell has a height X, a width Y, and an effective width (W) Z, then the second logic cell has a height 2X, a width Y, and W>2.5 Z.

Staggered stacked circuits with increased effective width

A stacked layer memory for a SRAM includes a first layer of the SRAM, including multiple transistors of a first type, and includes a second layer of the SRAM, having multiple transistors of a second type. The first and second layers are different layers stacked vertically. A width of individual SRAM cells of the stacked layer memory is defined at least by a pitch of a single transistor of the transistors of the first type and the transistors of the second type. A method for forming the stacked layer memory for the SRAM includes forming the first layer and the second layer. The first and second layers are different layers and are formed to be stacked vertically. A width of individual SRAM cells of the stacked layer memory is defined at least by a pitch of a single transistor of the transistors of the first and second types.

Stacked layer memory suitable for SRAM and having a long cell

A semiconductor device is provided that includes at least one stacked FET device including two top transistors stacked over a single bottom transistor. The at least one stacked FET includes a full gate cut structure that is used to separate different device areas from each other, a top gate cut structure that used to separate the two top transistors, and a bottom gate cut structure that is used to provide the single bottom transistor. The at least one FET device can be used to provide a SRAM containing six transistors.

Stacked FET SRAM

Embodiments of present invention provide a transistor structure. The transistor structure includes a first and a second transistor in a first transistor layer; a first and a second transistor in a second transistor layer, respectively, above the first and the second transistor in the first transistor layer; a metal routing layer between the first transistor layer and the second transistor layer; a first local interconnect connecting the first transistor of the first transistor layer to the metal routing layer; and a second local interconnect connecting the metal routing layer to the second transistor of the second transistor layer. A method of manufacturing the transistor structure is also provided.

Local interconnect for cross coupling

Embodiments of present invention provide a SRAM memory. The SRAM memory includes a frontside and a backside; a first pull-up (PU) transistor stacked over a first pull-down (PD) transistor; a second PU transistor stacked over a second PD transistor; a frontside cross-couple at the frontside, above the first and second PU transistors, that connects a first source/drain (S/D) region of the first PU transistor with a gate of the second PU transistor; and a backside cross-couple, at the backside underneath the first and second PD transistors, that connects a first S/D region of the second PD transistor with a gate of the first PD transistor. A method of manufacturing the SRAM memory is also provided.

SRAM with backside cross-couple

Embodiments are disclosed for a system. The system includes multiple tracks. Further, one track includes a power rail for a first voltage. The system also includes a first via, disposed beneath, and in electrical contact with, the power rail. The system additionally includes a first contact, beneath, and in electrical contact with, the first via. The system further includes a first field effect transistor (FET), beneath, and in electrical isolation with, the first contact. Additionally, the system includes a second FET, beneath, and in electrical contact with, the first FET. Further, the system includes a second contact, beneath, and in electrical contact with, the second FET. Also, the system includes a second via, beneath, and in electrical contact with, the second contact. The system additionally includes a buried power rail (BPR), beneath, and in electrical contact with, the second via, wherein the BPR comprises a second voltage.

Vertically-stacked field effect transistor cell

Growing community of inventors

Essex, VT, United States of America

Albert Manhee Chu