International Business Machines Corporation

Globalfoundries Inc.

Infineon Technologies North America Corp.

Other

Siemens Aktiengesellschaft

Qimonda Ag

Albert Manhee Chu

Brent A Anderson

Ruilong Xie

Junli Wang

Lawrence Alfred Clevenger

Daryl Michael Seitzer

Nicholas Anthony Lanzillo

Rohit Pradeep Shetty

Ravikumar Ramachandran

John Atkinson Fifield

Reinaldo Ariel Vega

Albert M Young

Myung-Hee Na

Carl John Radens

Wagdi William Abadeer

Thomas W Wyckoff

Dechao Guo

Kisik Choi

Frank David Ferraiolo

George Maria Braceras

Ronald A Piro

Jean-Marc Dortu

Jeffrey Scott Brown

Robert E Busch

Edward J Nowak

Robert J Gauthier, Jr

Hemanth Jagannathan

Julien Frougier

Heng Wu

Michael Richard Ouellette

JunJun Li

Harold Pilo

Emre Alptekin

Kafai Lai

Jason D Hibbeler

Mujahid Muhammad

Kevin William Gorman

David S Wolpert

Robert J Allen

Daniel Nelson Maynard

Michael S Gray

Robert F Walker

Ezra D B Hall

William R Griffin

Allan Robert Bertolet

Faye D Baker

Mervyn Y Tan

Manikandan Viswanath

Eric Eastman

Ximeng Guan

Jonathan B Ashbrook

Effendi Leobandung

Veeraraghavan S Basker

Balasubramanian Pranatharthiharan

Lars W Liebmann

Terence B Hook

Daniel Mark Dreps

Kevin Charles Gower

Huiming Bu

Robert C Wong

Joseph Andrew Iadanza

Rajasekhar Venigalla

Sean David Burns

John Christopher Arnold

Paul Christian Parries

Nazmul Habib

Ning Lu

Douglas Willard Stout

Christopher P Miller

Jay William Strane

Jason Eugene Stephens

Tao Li

Alexander Joel Suess

Leon Jacob Sigal

Somnath Ghosh

Daniel James Dechene

Kevin A Batson

Larry Wissel

Sagarika Mukesh

Kai Zhao

Seong-Dong Kim

Roger Paul Gregor

Alan C Thomas

Paul T Gutwin

Vikrant Kumar Chauhan

Eric Miller

Jason Edward Rotella

Laura R Darden

Eric D Johnson

Biswanath Senapati

Samuel K Weinstein

John G Petrovick, Jr

Jens Haetty

Michael Sofranko

William J Rensch

Teresa Thi Nguyen

Jane S Tu

Vidhi Zalani

Daryl M Seizter

One or more systems, devices, and/or methods of fabrication provided herein relate to reduced parasitic capacitance of power via bars. According to one embodiment, a semiconductor device can comprise a field-effect transistor (FET), and a power via bar coupled to a backside power rail, wherein the power via bar has greater height adjacent to a source and drain region of the field-effect transistor (FET) relative to a gate of the FET to mitigates parasitic capacitance within the device.

Reduced capacitance between power via bar and gates

A semiconductor structure including a gate contact above and in direct contact with a top surface of a gate, a backside wiring layer below a backside power delivery network, and a contact via extending between the gate contact and the backside wiring layer.

Backside self aligned skip via

According to the embodiment of the present invention, a semiconductor device includes a first nanodevice and a second nanodevice. The second nanodevice is located adjacent to and parallel to the first nanodevice along a first axis. The first nanodevice and the second nanodevice each include a first section, a second section, and a third section. A first gate cut region is located between the first sections of the first nanodevice and the second nanodevice. A middle gate cut region is located between the second sections of the first nanodevice and the second nanodevice. A third gate cut region is located between the third sections of the first nanodevice and the second nanodevice. The middle gate cut region has different dimensions along a second axis than the first gate cut region and the third gate cut region.

Different dimensions across active region for stronger via to backside power rail

A semiconductor device is provided. The semiconductor device includes a bottom field effect transistor (FET) including a bottom source-drain epitaxial layer formed on sides of the bottom FET; a top FET stacked over the bottom FET; a back-end-of-line (BEOL) layer formed on the top FET; a bottom gate contact formed in contact with the bottom FET and having an extending portion of the bottom gate contact that extends laterally over the bottom source-drain epitaxial layer; and a top gate contact formed in contact with the extending portion of the bottom gate contact and electrically connecting the bottom gate contact to the BEOL layer.

Stacked field effect transistor

Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a semiconductor wafer having a first transistor and a second transistor; a first source/drain (S/D) contact of the first transistor; a second S/D contact of the second transistor; and a cut region between the first S/D contact and the second S/D contact, wherein the cut region includes a liner of a first dielectric material and a filler of a second dielectric material that is different from the first dielectric material, the liner lining at least a part of the first S/D contact and a part of the second S/D contact, and the filler being directly adjacent to the liner and between the first S/D contact and the second S/D contact. A method of manufacturing the semiconductor structure is also provided.

Source/drain contact at tight cell boundary

A field effect transistor ('FET') stack, including a lower FET, and an upper FET, a first contact to a lower source drain of the lower FET, a first silicide between the first contact and the lower source drain, the first contact is adjacent to a vertical side surface of the lower source drain, a first overlap region between the first silicide and the first contact is less than a second overlap region between the first silicide and the first source drain. The first contact has a reverse tapper metal stud profile. Forming a first contact to a lower source drain of a lower FET of an FET stack, forming a first silicide between the first contact and the lower source drain, the first contact is adjacent to a vertical side surface of the lower source drain.

Subtractive source drain contact for stacked devices

A microelectronic structure comprises a first interconnect line at a first interconnect level, a second interconnect line at a second interconnect level, and at least one via connecting the first interconnect line at the first interconnect level to the second interconnect line at the second interconnect level. The at least one via comprises a vertical section and at least one horizontal section, the at least one horizontal section being in contact with at least a portion of one of a top surface of the first interconnect line and a bottom surface of the second interconnect line.

Interconnect structures with vias having vertical and horizontal sections

A structure is provided that includes a first metal level including a first metal line, a second metal level spaced apart from the first metal level and including a second metal line, and a first metal via structure connecting the first metal line to the second metal line. The first metal via structure directly contacts a sidewall surface and a horizontal surface of the first metal line.

Wrap around metal via structure

A vertical transport field effect transistor (VTFET) apparatus includes a fin-shaped channel structure; a gate stack that surrounds the channel structure; a top source/drain structure at a top end of the channel structure; a top interconnect layer above the top source/drain structure; a top contact that electrically connects the top source/drain structure to the top interconnect layer; a bottom source/drain structure at a bottom end of the channel structure; a backside interconnect layer below the bottom source/drain structure; and a backside contact that touches a bottom surface of the bottom source/drain structure and also touches a side surface of the bottom source/drain structure and electrically connects the bottom source/drain structure to the backside interconnect layer.

Vertical transport field effect transistor (VTFET) with backside wraparound contact

Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a stack of transistors with a first transistor on top of a second transistor, where a gate of the first transistor has a first width; a gate of the second transistor has a second width; and the first width is narrower than the second width, and where the first and the second transistor respectively have a first gate extension at a first side of the stack and a second gate extension at a second side of the stack, the first gate extension at the first side of the stack being narrower than the second gate extension at the second side of the stack, with the first side being opposite the second side. A method of manufacturing the semiconductor structure is also provided.

Asymmetric gate extension in stacked FET

A semiconductor structure including a vertical semiconductor channel region, a bottom source drain region arranged on a substrate at a bottom of the vertical semiconductor channel region, a metal gate disposed around the vertical semiconductor channel region, where a first portion of the metal gate extends above the vertical semiconductor channel region, and a gate contact entirely above the vertical semiconductor channel region.

Vertical transistor with reduced cell height

A semiconductor structure having improved performance is provided that includes a local enlarged via-to-backside power rail (VBPR) contact structure which connects a source/drain region of one field effect transistor (FET) to a backside power rail.

Local enlarged via-to-backside power rail

A microelectronic structure including a plurality of lower transistors and a plurality of upper transistor, where each of the plurality of lower transistors and the plurality of upper transistors includes a plurality of channel. Where an upper center vertical axis of each of the plurality of upper transistors is staggered from a lower center vertical axis of each of the lower transistors. A lower gate cut is located between each of the plurality of lower transistors. A first upper gate cut located adjacent to a first upper transistor of the plurality of upper transistors, where the first upper gate cut is in direct contact with a plurality of first channels of the first upper transistor.

Method and structure of forming independent contact for staggered CFET

A semiconductor memory cell comprising six vertical-transport field-effect transistors (VTFET) on a wafer. The six VTFET are in a first layer. The six VTFET are in a first row.

High density static random-access memory

Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a metal level, the metal level includes a metal strip including a notch at a side of the metal strip or a pass-through inside the metal strip, wherein the notch or the pass-through is at least partially filled with a dielectric material. The metal level further includes a conductive wiring that vertically passes through the metal strip. The conductive wiring is at least partially inside the notch or inside the pass-through and is insulated from the metal strip by the dielectric material. Methods of manufacturing the semiconductor structure are also provided.

Pass-through wiring in notched interconnect

Growing community of inventors

Essex, VT, United States of America

Albert Manhee Chu