Marvell Asia Pte., Ltd.

Cavium, Inc.

Albert Ma

Wilson Parkhurst Snyder, Ii

Shubhendu Sekhar Mukherjee

Mike Bertone

Anna Kujtkowski

Jason D Zebchuk

Aadeetya Shreedhar

Joseph Featherston

Varada Ramesh Ogale

Paul G Scrobohaci

Manan Salvi

Oded Tsur

A system and corresponding method perform large memory transaction (LMT) stores. The system comprises a processor associated with a data-processing width and a processor accelerator. The processor accelerator performs a LMT store of a data set to a coprocessor in response to an instruction from the processor targeting the coprocessor. The data set corresponds to the instruction. The LMT store includes storing data from the data set, atomically, to the coprocessor based on a LMT line (LMTLINE). The LMTLINE is wider than the data-processing width. The processor accelerator sends, to the processor, a response to the instruction. The response is based on completion of the LMT store of the data set in its entirety. The processor accelerator enables the processor to perform useful work in parallel with the LMT store, thereby improving processing performance of the processor.

System and method for large memory transaction (LMT) stores

A circuit and corresponding method provide a translation lookaside buffer (TLB) implementation. The circuit comprises a plurality of TLB banks and TLB logic. The TLB logic computes a plurality of hash values of a tag included in a memory request. The TLB logic locates, based on hash values of the plurality of hash values computed, a contiguous translation entry (TE) and a non-contiguous TE in different TLB banks of the plurality of TLB banks. The TLB logic determines a result by comparing the tag with the contiguous TE located and by comparing the tag with the non-contiguous TE located. The TLB logic outputs the result determined toward servicing the memory request. The TLB logic advantageously enables the TLB implementation to support contiguous pages using standard random-access memories for the plurality of TLB banks.

Circuit and method for translation lookaside buffer (TLB) implementation

A circuit and corresponding method map memory addresses onto cache locations within set-associative (SA) caches of various cache sizes. The circuit comprises a modulo-arithmetic circuit that performs a plurality of modulo operations on an input memory address and produces a plurality of modulus results based on the plurality of modulo operations performed. The plurality of modulo operations performed are based on a cache size associated with an SA cache. The circuit further comprises a multiplexer circuit and an output circuit. The multiplexer circuit outputs selected modulus results by selecting modulus results from among the plurality of modulus results produced. The selecting is based on the cache size. The output circuit outputs a cache location within the SA cache based on the selected modulus results and the cache size. Such mapping of the input memory address onto the cache location is performed at a lower cost relative to a general-purpose divider.

System and method for mapping memory addresses to locations in set-associative caches

A method of translating a virtual address into a physical memory address in an ARM System Memory Management Unit version 3 (SMMUv3) system includes searching a Configuration Cache memory for a matching tag that matches an associated tag upon receiving the virtual address and the associated tag, and extracting, in a single memory lookup cycle, a matching data field associated with the matching tag when the matching tag is found in the Configuration Cache memory. A matching data field of the Configuration Cache memory includes a matching Stream Table Entry (STE) and a matching Context Descriptor (CD), both associated with the matching tag. The Configuration Cache memory may be configured as a content-addressable memory. The method further includes storing entries associated with a multiple memory lookup cycle virtual address-to-physical address translation into the Configuration Cache memory, each of the entries including a tag, an associated STE and an associated CD.

Configuration cache for the ARM SMMUv3

Execution of the memory instructions is managed using memory management circuitry including a first cache that stores a plurality of the mappings in the page table, and a second cache that stores entries based on virtual addresses. The memory management circuitry executes operations from the one or more modules, including, in response to a first operation that invalidates at least a first virtual address, selectively ordering each of a plurality of in progress operations that were in progress when the first operation was received by the memory management circuitry, wherein a position in the ordering of a particular in progress operation depends on either or both of: (1) which of one or more modules initiated the particular in progress operation, or (2) whether or not the particular in progress operation provides results to the first cache or second cache.

Instruction ordering for in-progress operations

In an embodiment, a method of providing quality of service (QoS) to at least one resource of a hardware processor includes providing, in a memory of the hardware processor, a context including at least one quality of service parameter and allocating access to the at least one resource of the hardware processor based on the quality of service parameter of the context, a device identifier, a virtual machine identifier, and the context.

Sharing resources in a multi-context computing system

In an embodiment, interfacing a pipeline with two or more interfaces in a hardware processor includes providing a single pipeline in a hardware processor. The single pipeline presents at least two visible units. The single pipeline includes replicated architecturally visible structures, shared logic resources, and shared architecturally hidden structures. The method further includes receiving a request from one of a plurality of interfaces at one of the visible units. The method also includes tagging the request with an identifier based on the one of the at least two visible units that received the request. The method further includes processing the request in the single pipeline by propagating the request through the single pipeline through the replicated architecturally visible structures that correspond with the identifier.

Approach for interfacing a pipeline with two or more interfaces in a processor

In an embodiment, a method include, in a hardware processor, producing, by a block of hardware logic resources, a constrained randomly generated or pseudo-randomly generated number (CRGN) based on a bit mask stored in a register memory.

Distributing resource requests in a computing system

A core executes memory instructions. A memory management unit (MMU) coupled to the core includes a first cache that stores a plurality of final mappings of a hierarchical page table, a page table walker that traverses levels of the page table to provide intermediate results associated with respective levels for determining the final mappings, and a second cache that stores a limited number of intermediate results provided by the page table walker. The MMU compares a portion of the first virtual address to portions of entries in the second cache, in response to a request from the core to invalidate a first virtual address, based on a match criterion that depends on the level associated with each intermediate result stored in an entry in the second cache, and removes any entries in the second cache that satisfy the match criterion.

Growing community of inventors

Belmont, MA, United States of America

Albert Ma