International Business Machines Corporation

Massachusetts Institute of Technology

Other

Albert M Young

Junli Wang

Brent A Anderson

Ruilong Xie

Roy Rongqing Yu

Fei Liu

Matthew R Wordeman

Mukta G Farooq

Sampath Purushothaman

Subramanian Srikanteswara Iyer

Albert Manhee Chu

Steven John Koester

Robert Hannon

Chung H Lam

Leland Chang

Kuan-Neng Chen

Lia Krusin-Elbaum

Mark Alexander Hollis

James Douglas Harper

Dechao Guo

Balasubramanian Pranatharthiharan

Su Chen Fan

Kisik Choi

Anna Wanda Topol

Todd H Rider

Trina Rae Vian

Martha Susan Petrovick

Richard Hart Mathews

Eric D Schwoebel

Bernadette Johnson

Frances E Nargi

Timothy Stephens

Ann Rundell

Linda Marie Mendenhall

Paul William Coteus

Takeshi Nogami

Kerry Bernstein

Daniel Joseph Friedman

Philip George Emma

Robert K Montoye

Edmund Juris Sprogis

Ravikumar Ramachandran

Dennis Merton Newns

Ruchir Puri

Michael Jay Shapiro

Bruce Kenneth Furman

Cornelia K Tsang

Bruce Gordon Elmegreen

Mark B Ritter

Sarah Huffsmith Knickerbocker

Tao Li

Jeannine Madelyn Trewhella

Jae-sun Seo

Ibrahim M Elfadel

Tsung-Sheng Kang

Ardasheir Rahman

Edward M DeMulder

Kangguo Cheng

Chen Zhang

Shogo Mochizuki

Julien Frougier

Terence B Hook

Ruqiang Bao

Heng Wu

Huiming Bu

Meikei Ieong

Indira P Seshadri

Stuart A Sieg

John Christopher Arnold

Leathen Shi

Douglas C La Tulipe, Jr

Gen Tsutsui

Somnath Ghosh

Sagarika Mukesh

Kai Zhao

James Vichiconti

Laura T Bortolin

Lalitha Parameswaran

Johanna Bobrow

Vidhi Zalani

Eric David Schwoebel

Frances Ellen Nargi

Todd Harrison Rider

A semiconductor device is provided. The semiconductor device includes a bottom field effect transistor (FET) including a bottom source-drain epitaxial layer formed on sides of the bottom FET; a top FET stacked over the bottom FET; a back-end-of-line (BEOL) layer formed on the top FET; a bottom gate contact formed in contact with the bottom FET and having an extending portion of the bottom gate contact that extends laterally over the bottom source-drain epitaxial layer; and a top gate contact formed in contact with the extending portion of the bottom gate contact and electrically connecting the bottom gate contact to the BEOL layer.

Stacked field effect transistor

A field effect transistor ('FET') stack, including a lower FET, and an upper FET, a first contact to a lower source drain of the lower FET, a first silicide between the first contact and the lower source drain, the first contact is adjacent to a vertical side surface of the lower source drain, a first overlap region between the first silicide and the first contact is less than a second overlap region between the first silicide and the first source drain. The first contact has a reverse tapper metal stud profile. Forming a first contact to a lower source drain of a lower FET of an FET stack, forming a first silicide between the first contact and the lower source drain, the first contact is adjacent to a vertical side surface of the lower source drain.

Subtractive source drain contact for stacked devices

A microelectronic structure including a first stacked FET device that includes a first bottom FET device and a first upper FET device. The first bottom FET device include a plurality of first bottom channel layers, and the first upper FET device includes a plurality of first upper channel layers. A bottom gate that surrounds the plurality of first bottom channel layers and an upper gate that surrounds the plurality of first upper channel layers. A gate protrusion that extends downwards from the backside of the upper gate to connected to the bottom gate. The gate protrusion partially overlaps with a bottom gate cut region of the first bottom stacked FET device, and the gate protrusion partially overlaps with an upper gate cut region of the first upper stacked FET device.

Stacked FET with extremely small cell height

An approach forming semiconductor structure composed of one or more stacked semiconductor devices that include at least a top semiconductor device, a bottom semiconductor device under the top semiconductor, and contacts to each of the semiconductor devices. The approach provides a stacked semiconductor structure where the bottom semiconductor device is wider than the top semiconductor device. The approach also provides the stacked semiconductor structure where the width of the top semiconductor device is the same as the width of the bottom semiconductor device. The approach includes forming a contact to a side of the bottom semiconductor device when the width of the top semiconductor device is the same as the bottom semiconductor device. The approach includes forming a contact to epitaxy grown on a portion of the top and a side of the bottom semiconductor device when the bottom semiconductor device is larger than the top semiconductor device.

Bottom contact with self-aligned spacer for stacked semiconductor devices

A microelectronic structure including a plurality of lower transistors and a plurality of upper transistor, where each of the plurality of lower transistors and the plurality of upper transistors includes a plurality of channel. Where an upper center vertical axis of each of the plurality of upper transistors is staggered from a lower center vertical axis of each of the lower transistors. A lower gate cut is located between each of the plurality of lower transistors. A first upper gate cut located adjacent to a first upper transistor of the plurality of upper transistors, where the first upper gate cut is in direct contact with a plurality of first channels of the first upper transistor.

Method and structure of forming independent contact for staggered CFET

Embodiments of present invention provide a transistor structure. The transistor structure includes a first and a second transistor in a first transistor layer; a first and a second transistor in a second transistor layer, respectively, above the first and the second transistor in the first transistor layer; a metal routing layer between the first transistor layer and the second transistor layer; a first local interconnect connecting the first transistor of the first transistor layer to the metal routing layer; and a second local interconnect connecting the metal routing layer to the second transistor of the second transistor layer. A method of manufacturing the transistor structure is also provided.

Local interconnect for cross coupling

A field effect device is provided. The field effect device includes a lower active gate structure on a substrate, and a first lower source/drain on a first side of the lower active gate structure. The field effect device further includes a second lower source/drain on a second side of the lower active gate structure opposite the first side, and a first lower source/drain contact interface on the first lower source/drain. The field effect device further includes a first upper source/drain on the first side of an upper active gate structure, and a second upper source/drain on the second side of the upper active gate structure opposite the first side. The field effect device further a shared source/drain contact forming an electrical connection between the first lower source/drain and the first upper source/drain; and a lower source/drain contact forming an electrical connection to the second lower source/drain.

Middle of line structure with stacked devices

Embodiments are disclosed for a system. The system includes multiple tracks. Further, one track includes a power rail for a first voltage. The system also includes a first via, disposed beneath, and in electrical contact with, the power rail. The system additionally includes a first contact, beneath, and in electrical contact with, the first via. The system further includes a first field effect transistor (FET), beneath, and in electrical isolation with, the first contact. Additionally, the system includes a second FET, beneath, and in electrical contact with, the first FET. Further, the system includes a second contact, beneath, and in electrical contact with, the second FET. Also, the system includes a second via, beneath, and in electrical contact with, the second contact. The system additionally includes a buried power rail (BPR), beneath, and in electrical contact with, the second via, wherein the BPR comprises a second voltage.

Vertically-stacked field effect transistor cell

A device comprises a first interconnect structure, a second interconnect structure, a first cell comprising a first transistor, a second cell comprising a second transistor, a first contact connecting a source/drain element of the first transistor to the first interconnect structure, and second contact connecting a source/drain element of the second transistor to the second interconnect structure. The first cell is disposed adjacent to the second cell with the first transistor disposed adjacent to the second transistor. The first and second cells are disposed between the first and second interconnect structures.

Backside power rails and power distribution network for density scaling

A high aspect ratio contact structure formed within a dielectric material includes a top portion and a bottom portion. The top portion of the contact structure includes a tapering profile towards the bottom portion. A first metal stack surrounded by an inner spacer is located within the top portion of the contact structure and a second metal stack is located within the bottom portion of the contact structure. A width of the bottom portion of the contact structure is greater than a minimum width of the top portion of the contact structure.

High aspect ratio contact structure with multiple metal stacks

A semiconductor structure includes a first transistor device comprising a plurality of channel regions. The semiconductor structure further includes a second transistor device comprising a plurality of channel regions. The first transistor device and the second transistor device are disposed in a stacked configuration. The plurality of channel regions of the first transistor device are disposed in a staggered configuration relative to the plurality of channel regions of the second transistor device.

Staggered stacked semiconductor devices

A semiconductor device includes a dielectric isolation layer, a plurality of gates formed above the dielectric isolation layer, a plurality of source/drain regions above the dielectric isolation layer between the plurality of gates, and at least one contact placeholder for a backside contact. The at least one contact placeholder contacts a bottom surface of a first source/drain region of the plurality of source/drain regions. The semiconductor device further includes at least one backside contact contacting a bottom surface of a second source/drain region of the plurality of source/drain regions, and a buried power rail arranged beneath, and contacting the at least one backside contact.

Backside electrical contacts to buried power rails

A memory device includes a first field effect transistor (FET) stack on a first bottom source/drain region, which includes a first vertical transport field effect transistor (VTFET) device between a second VTFET device and the first source/drain region, and a second FET stack on a second bottom source/drain region, which includes a third VTFET device between a fourth VTFET device and the bottom source/drain region. The memory device includes a third FET stack on a third bottom source/drain region, which includes a fifth VTFET between a sixth VTFET and the third source/drain region, which is laterally adjacent to the first and second source/drain regions. The memory device includes a first electrical connection interconnecting a gate structure of the third VTFET with a gate structure of the fifth VTFET, and a second electrical connection interconnecting a gate structure of the second VTFET with a gate structure of the sixth VTFET.

Static random access memory using vertical transport field effect transistors

A method of manufacturing a semiconductor device is provided. The method includes forming a first trench partially through a first substrate from a first side of the first substrate. The method also includes widening a bottom portion of the first trench to form a lateral footing area of the first trench. The method includes forming a first metallization in the first trench; forming a second trench through a second substrate from a second side of the second substrate to expose at least a portion of first metallization in an area corresponding to the lateral footing area of the first trench, the second side being opposite to the first side. The method also includes forming a second metallization in the second trench in contact with the first metallization.

Backside power rail integration

A technique relates to a semiconductor device. A source/drain layer is formed. Fins with gate stacks are formed in a fill material, a dummy fin template including at least one fin of the fins and at least one gate stack of the gate stacks, the fins being formed on the source/drain layer. A trench is formed through the fill material by removing the dummy fin template, such that a portion of the source/drain layer is exposed in the trench. A source/drain metal contact is formed on the portion of the source/drain layer in the trench.

Dummy fin template to form a self-aligned metal contact for output of vertical transport field effect transistor

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Fishkill, NY, United States of America

Albert M Young