Marvell International Limited

Marvellworld Trade Ltd.

Linear Technology Corporation

Other

Winbond Electronics Corporation

Analog Devices International Unlimited Company

Megic Corporation

Weride Corp.

Marvell Semiconductor, Inc.

Albert M Wu

Runzi Chang

Winston Lee

Pantas Sutardja

Peter W Lee

Chien-Chuan Wei

Shiann-Ming Liou

Sehat Sutardja

Chuan-Cheng Cheng

Roawen Chen

Scott Wu

Shuhua Yu

Steven M Pietkiewicz

Chorng-Lii Liou

Huahung Kao

Chung Chyung Han

Wanfeng Zhang

Robert C Dobkin

Loc Bao Hoang

Chenglin Liu

Long-Ching Wang

Dah-Bin Kao

Tung-Yi Chan

Abdul Elaydi

Jeffrey Schenkel

Hungchi Chen

Nelson Tam

Chung Chyung (Justin) Han

Bruce Wang

Chiping Ai

Mou-Shiung Lin

Jin-Yuan Lee

Poh Boon Leong

Zafer S Kutlu

Weidan Li

Mathew Todd Wich

Yiqing Yang

John David Brazzle

Qiu Jin

Matthew Anthony Topp

Hua Zhong

Hyun Jeong Shin

Zhiyuan Zuo

Tianming Lu

Zeyin Zhang

Xuanzhu Lin

Xiong Wu

Xiaohua Su

An apparatus and a method for controlling a velocity of an autonomous driving vehicle is provided. The method includes steps of: obtaining information of an environment surrounding the vehicle when an obstacle is detected to be on a planning path of the vehicle; obtaining an initial reference velocity profile of the vehicle; determining a safety factor based on the initial reference velocity profile, the information of the environment and information of the vehicle, wherein the safety factor at least comprises a safety distance between the vehicle and the obstacle for the vehicle to follow the obstacle; determining an optimized reference velocity profile based on the information of the environment, the information of the vehicle and the safety factor; and performing the step of determining the safety factor by using the optimized reference velocity profile as the initial reference velocity profile and the step of determining the optimized reference velocity iteratively.

Apparatus and method for controlling velocity of autonomous driving vehicle, and storage medium

A packaging technology in which power switching elements, such as field-effect transistors (FETs), can be oriented in a vertical position relative to the printed circuit board (PCB) on which the product is mounted. The power die including the switching element(s) can essentially stand 'on end' so that they take up very little PCB area. Multiple dies can be positioned this way, and the dies can be attached to a heat sink structure, which is designed to take the heat generated by the dies onto the top of the package. The heat sink structure can be attached to a structure to route the power and analog signals properly to the desired pins/leads/balls of the finished product. Using these techniques can result in a significant increase in the power density (both PCB space and solution volume) of power switching elements, e.g., FETs.

Three-dimensional packaging techniques for power FET density improvement

An energy storage stack balancing circuit may balance a set of serially connected energy storage devices. An electronic switching system may control the delivery of energy into and out of the inductor. A controller may control the electronic switching system so as to cause energy to be transferred: from one of the energy storage devices into the inductor and then out of the inductor and into a different one, a subset, or all of the energy storage devices; or from a subset of the energy storage devices into the inductor and then out of the inductor and into one, a different subset, or all of the energy storage devices; or from all of the energy storage devices into the inductor and then out of the inductor and into one or a subset the energy storage devices.

Energy storage device stack balancing using switched inductor background

Embodiments of the present disclosure provide an apparatus comprising a semiconductor substrate having a first surface, a second surface that is disposed opposite to the first surface, wherein at least a portion of the first surface is recessed to form a recessed region of the semiconductor substrate, and one or more vias formed in the recessed region of the semiconductor substrate to provide an electrical or thermal pathway between the first surface and the second surface of the semiconductor substrate, and a die coupled to the semiconductor substrate, the die being electrically coupled to the one or more vias formed in the recessed region of the semiconductor substrate. Other embodiments may be described and/or claimed.

Package assembly including a semiconductor substrate in which a first portion of a surface of the semiconductor substrate is recessed relative to a second portion of the surface of the semiconductor substrate to form a recessed region in the semiconductor substrate

Some of the embodiments of the present disclosure provide a semiconductor package interposer comprising a substrate having a first surface and a second surface, a plurality of vias extending between the first surface and the second surface of the substrate, the plurality of vias electrically connecting electrical connectors or circuitry on the first surface of the substrate to electrical connectors or circuitry on the second surface of the substrate, and metal plugs at least partially filling the plurality of vias. At least one of (i) the first surface or (ii) the second surface of the substrate includes depressions at distal ends of the metal plugs.

Method and apparatus for improving the reliability of a connection to a via in a substrate

In an embodiment, there is provided a method of creating a package, the method comprising: providing an initial substrate, wherein the initial substrate comprises a carrier foil, a functional copper foil, and an interface release layer between the carrier foil and the functional copper foil; building up copper portions on the functional copper foil; attaching a chip to a first copper portion; coupling the chip to a second copper portion; encapsulating at least the chip and the copper portions with a mold; and removing the carrier foil and interface release layer.

Methods of making packages using thin Cu foil supported by carrier Cu foil

A system including a resistive element of a memory cell and a device to access the resistive element of the memory cell. The resistive element includes (i) a first electrode, and (ii) a second electrode. The device includes (i) a first terminal connected to a first contact, and (i) a second terminal connected to a second contact. One or more of the first contact and the second contact of the device is respectively connected to one or more of the first electrode and the second electrode of the resistive element via a third contact. A size of the third contact decreases from the one or more of the first contact and the second contact of the device to the one or more of the first electrode and the second electrode of the resistive element of the memory cell.

Resistive random access memory cell structure

A circuit including a first die, an integrated passive device and a second layer. The first die includes a first substrate and active devices. The integrated passive device includes a first layer, a second substrate and passive devices. The second substrate includes vias. The passive devices are implemented at least on the first layer or the second substrate. A resistivity per unit area of the second substrate is greater than a resistivity per unit area of the first substrate. The second layer is disposed between the first die and the integrated passive device. The second layer includes pillars. Each of the pillars connects a corresponding one of the active devices to (i) one of the vias, or (ii) one of the passive devices. The first die, the integrated passive device and the second layer are disposed relative to each other to form a stack.

Method and apparatus for incorporating passive devices in an integrated passive device separate from a die

Embodiments of the present disclosure provide a method, comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming one or more vias in the first surface of the semiconductor substrate, the one or more vias initially passing through only a portion of the semiconductor substrate without reaching the second surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, the redistribution layer being electrically coupled to the one or more vias, coupling one or more dies to the redistribution layer, forming a molding compound to encapsulate at least a portion of the one or more dies, and recessing the second surface of the semiconductor substrate to expose the one or more vias. Other embodiments may be described and/or claimed.

Recessed semiconductor substrates and associated techniques

Embodiments of the present disclosure provide a package comprising a die attach pad, a die disposed on the die attach pad and a leadframe. The leadframe includes an opening defined therein that exposes a bottom surface of the die attach pad. The leadframe comprises a plurality of bond pads that are exposed at a bottom surface of the leadframe and a plurality of traces that are exposed at the bottom surface of the leadframe. Each trace of the plurality of traces is coupled to a corresponding bond pad of the plurality of bond pads. At least some of the traces are coupled to the die at top surfaces of the at least some of the traces. The leadframe also comprises a plurality of first insulated barriers. Each first insulated barrier is located between (i) a corresponding trace and (ii) a corresponding bond pad coupled to the corresponding trace.

Method and apparatus for mounting solder balls to an exposed pad or terminal of a semiconductor package

A power converting system produces an input signal regulated with respect to an input signal. The power converting system has a first inductive element having a first node coupled to an input node, and a second inductive element having a first node coupled to an output node. A first switching element is coupled to a second node of the first inductive element. A first capacitive element is coupled between the second node of the first inductive element and of the second inductive element. A control circuit sets a duty cycle of the first switching element to a first value for providing the output signal of a first polarity responsive to the input signal of the first polarity, and to set the duty cycle of the first switching element to a second value for providing the output signal of a second polarity responsive to the input signal of the first polarity.

Power converter for generating both positive and negative output signals

Embodiments of the present disclosure provide a method that includes providing a semiconductor substrate comprising a semiconductor material, forming a dielectric layer on the semiconductor substrate, forming an interconnect layer on the dielectric layer, attaching a semiconductor die to the semiconductor substrate, and electrically coupling an active side of the semiconductor die to the interconnect layer, the interconnect layer to route electrical signals of the semiconductor die. Other embodiments may be described and/or claimed.

Package assembly having a semiconductor substrate

A resistive random access memory system includes a plurality of bitlines, a plurality of wordlines, and an array of resistive random access memory cells. Each of the resistive random access memory cells in the array includes a transistor and a resistive random access memory element connected in a common gate configuration.

Systems and methods for increasing the read sensitivity of a resistive random access memory (RRAM)

Methods and structures for transistors having reduced source contact to gate spacings in semiconductor devices are disclosed. In one embodiment, a method of forming a transistor can include: forming a gate over an active area of the transistor; forming source and drain regions aligned to the gate in the active area; forming source and drain contacts over the source and drain regions, where a spacing from the gate to the source contact of the transistor is less than a spacing from the gate to the drain contact of the transistor; and using one or more modified masks for forming doping profiles for the source region and the drain region.

Reducing source contact to gate spacing to decrease transistor pitch

Growing community of inventors

Sunnyvale, CA, United States of America

Albert M Wu