Other

France Telecom

Centre National D'etudes Des Telecommunications

Etat Francais Represente Par Le Ministre Des Postes, Telecommunications

L'etat Francais, Represente Par Le Ministre Des Ptt, Centre National

French State Represented by the Minister of the Post, Telecommunications

Etat Francais Represente Par Le Ministre Des Postes Et Telecommunications

L'etat Francais Represente Par Le Ministre Des P.t.t.

Albert Lespagnol

Jean-Paul Quinquis

Michel Servel

Jean-Paul Quinouis

Jacques Kerberenes

Jacques Y Kerberenes

A frame switching relay switches frames between input and output paths by multiplexing of the paths at frame cell level. A frame is divided into cells having a constant number of bits, whereas the frames are of variable length. The switching relay only retransmits frames that have been completely written in the buffer memory. A context memory preserves the address of the first cell at the start of the writing of a frame in the buffer memory, and memorizes the address of the output path for which the frame is destined, until the frame is completely written. A checking circuit checks that the writing of the frame does not cause an 'overflow' in the buffer memory, by updating the number of cells awaiting reading and respectively associated with the output paths. If there is no overflow, the address of the first cell of the frame is written in one of the address queues as a function of the destination output path address. The frame is subsequently read by incrementation of the address of the first cell until the end of the frame is detected.

Frame switching relay for asynchronous digital network

A communication system is designed to equip an asynchronous time-division network and to enable terminals linked to the network to communicate in the no-connection mode. The system comprises a ring management device and components distributed among the terminals and interfacing the terminals with a virtual ring for managing the production, reception and transmission of data cells. The ring management device is linked via the network to each of the terminals in order to control the connection/disconnection requests coming from the terminals and to supply information concerning cell routing to the terminals linked to the ring. A terminal has a particular role as a pilot for regulating the rate of the data cells in the virtual ring. Another purpose of the pilot terminal is to eliminate the altered cells. Furthermore, there is provided in each of the terminals a device for limiting its rate to a maximum value.

Complementary communication system in the no-connection mode for

A first switching network embodying the invention is a subscriber installation having a chain structure. In the network, the switching is distributed over a plurality of switches each connecting a terminal to the network. A second embodiment is a business network having a star-chain structure and comprising a plurality of sub-networks of chain type. The sub-networks are star connected to central switches which operate in a load sharing mode. According to the method embodying the invention, the terminals connected to the network assume themselves the responsibility for determining communication routes through the network. During a communication set-up phase, caller and callee terminals transmit call packets which are disseminated to all terminals in order to measure two so-called 'distances' respectively between the caller and the callee and between the callee and the caller. These distances are after included in data packets for routing said packets.

Routing method and packet switching networks having a distance indicator

The circuit embodying the invention comprises a pointer memory memorizing J=16 decremented write pointers associated with J=16 buffer queues. A channelling word supplied conjointly to incoming data and indicating the buffer queue in which this data is to be written, addresses the corresponding decremented write pointer. The write pointer and the channelling word form a write address for a buffer memory used as a medium for the J=16 queues. A comparator detects equality between the write pointer and the read pointer and in this case inhibits the acceptance of the incoming data which would overlay data not yet read. Logic means associated with the comparator control the updating, by possible incrementation, of the write pointer values contained in the pointer memory, after each data read in the buffer queues. This circuit is particularly well suited for use in an asynchronous self-channelling packet time-division switching system.

Buffer queue write pointer control circuit notably for self-channelling

The packet flow of each virtual circuit is measured and compared to an allocated average value. At each transmission authorization request (DAE'), when found to be less than the average value, a positive difference brings about an authorization to transmit and is translated into a right to transmit which is proportional to the time span since the previous request, the right to transmit being accumulated. When it is found to be greater than the average value, a negative difference brings about, if the number of accumulated transmission rights is positive, on one hand, the authorization to transmit and, on the other hand, a decrementing of the accumulated number, and if the accumulated number is nil, a refusal of authorization to transmit. Some examples of systems carrying out the process are described. The process and systems are applicable in particular to packets carried by asynchronous time multiplexers.

Method and system of control of flow of data packets

The apparatus is designed to use a single transmission medium to multiplex frames consisting of any number of bits of different origins which have previously passed through an asynchronous time-division network and are delivered in the form of packets of fixed length interlaced by an asynchronous time-division multiplex. A detection and write management circuit receives the packets and writes them in a packet memory as and when they arrive. In parallel with the writing of the packets, the addresses of the memory cell having memorized the packets of a given frame are written in the form of a string of frame addresses in a second memory. After complete writing of a frame in the first memory, a frame read and transmission circuit completely reads the frame using the corresponding address string and transmits it in serial form on the transmission medium. Packing words such as flags are inserted between the frames read.

Apparatus for reconstructing and multiplexing frames of various origins

A system for switching information packets assigned with two levels of semantic priority between entering time multiplex lines and outgoing time multiplex lines, a storage address of a packet in a buffer memory of the system being stored in a queueing file associated with each outgoing time multiplex line designated to transmit the packet, comprising a field point (state) memory whose words each are comprised of as many bits as there are outgoing time multiplex lines, the addresses of the the field point memory corresponding to those of the buffer memory, each bit of the words being at '1' when the packets stored at the same address as the words and designated for an outgoing time multiplex line corresponds to a high level semantic priority bit and has not yet been transmitted by the outgoing multiplex line concerned, each packet storage address being chosen from the addresses of the field point memory addressing all bits of which are at '0'.

Growing community of inventors

Perros-Guirec, France

Albert Lespagnol