Tsinghua University

Albert Lee

Meng-Fan Chang

Chien-Chen Lin

Chieh-Pu Lo

Provided is a non-volatile latch, which includes a latch circuit, a first switch circuit, a non-volatile memory device, a second switch circuit and a third switch circuit. A first terminal of the first switch circuit is coupled to a first output terminal of the latch circuit. The first switch circuit is turned off in a normal operation period. A first terminal of the non-volatile memory device is coupled to a second terminal of the first switch circuit. A second terminal of the non-volatile memory device is coupled to a programming voltage via the second switch circuit. In a store period, according to latched data of the latch circuit and a state transformation condition of the non-volatile memory device, the third switch circuit can dynamically determine whether to couple the first terminal of the non-volatile memory device to a reference voltage.

Non-volatile latch

A non-volatile SRAM cell comprises a first inverter, a second inverter, a first access transistor, a second access transistor, and a variable resistive element. The first inverter voltage is supplied by a first differential supply. The second inverter voltage is supplied by a second differential supply. The variable resistive element coupling with a third access transistor in series is coupled to the first output node. The non-volatile SRAM cell operates in a restore operation comprising a dual supply initialization phase and a pulse-overwrite phase. During the dual supply initialization phase, the first differential supply increases before the second differential supply so as to initialize the first output node to a logic state. During the pulse-overwrite phase, the third access transistor is turned on for a switch period in order to discharge/charge the first output node.

Non-volatile static random access memory using a 7T1R cell with initialization and pulse overwrite

A cell for a non-volatile ternary content-addressable (TCAM) memory is provided. The cell comprises a first variable resistive element, a first transistor and a charge control transistor. Two terminals of the first variable resistive element are respectively electrically coupled to a first search-line and a storage node. A drain electrode of the first transistor is electrically coupled to the storage node. A source electrode of the first transistor is electrically coupled to a low-side search-line. A gate electrode of the charge control transistor coupled to a match-line is electrically coupled to the storage node. When the cell operates in a search phase and the first transistor is turned on, a pulse voltage is applied across the first search-line and the low-side search-line for determining whether the voltage of the storage node is larger than a match threshold during the period of the pulse.

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Taipei, Taiwan

Albert Lee