Inston, Inc.

Albert Lee

Hochul Lee

Kang-Lung Wang

Systems and methods for reducing write error rate in MeRAM applications in accordance with various embodiments of the invention are illustrated. One embodiment includes a method for a writing mechanism for a magnetoelectric random access memory cell, the method including applying a voltage of a given polarity for a given period of time across a magnetoelectric junction bit of the magnetoelectric random access memory cell, wherein application of the voltage of the given polarity across the magnetoelectric junction bit reduces the perpendicular magnetic anisotropy and magnetic coercivity of the ferromagnetic free layer through a voltage controlled magnetic anisotropy effect, and lowering the applied voltage of the given polarity before the end of the given period of time, wherein the given period of time is approximately half of a precessional period of the ferromagnetic free layer.

Systems and methods for optimizing magnetic torque and pulse shaping for reducing write error rate in magnetoelectric random access memory

Reverse pulse schemes for reducing write error rate in magnetoelectric random access memory applications can be implemented in many different ways in accordance with various embodiments of the invention. One embodiment includes a method for a writing mechanism for a magnetoelectric random access memory cell, the method including applying a voltage of a given polarity for a period of time across a magnetoelectric junction bit of the magnetoelectric random access memory cell and applying a voltage of a polarity opposite the given polarity across the magnetoelectric junction bit at the end of the application of the voltage of the given polarity, wherein application of the voltage of the given polarity across the magnetoelectric junction bit reduces the perpendicular magnetic anisotropy and magnetic coercivity of the ferromagnetic free layer through a voltage controlled magnetic anisotropy effect.

Systems and methods for reducing write error rate in magnetoelectric random access memory through pulse sharpening and reverse pulse schemes

A sensing circuit includes a first sensing terminal, a second sensing terminal, a second grounding terminal, and a second grounding terminal. The first sensing terminal is connected to a source electrode of a transistor of a memory macro through a bit line. The second sensing terminal is electrically connected to a drain electrode of the transistor of the memory marco through a resistive memory device to a source line, and is not continuously connected to the grounding voltage. The first grounding terminal is used as a reference voltage of a voltage of the first sensing terminal. The second grounding terminal is used as a reference voltage of a voltage of the second sensing terminal. The sensing circuit outputs a sensing signal according to a voltage difference between the first sensing terminal and the second sensing terminal.

Sensing circuit and memory using thereof

The present disclosure provides a calibration method for a nonvolatile memory device having a plurality of unit cells, each of the unit cells corresponding to a word line and a bit line of the nonvolatile memory device. The calibration method includes: calibrating a word signal pulse of each of the word lines with a first calibration value corresponding to the word line; calibrating a bit signal pulse of each of the bit lines with a second calibration value corresponding to the bit line; and calibrating each of the unit cells according to the word line and the bit line corresponding to the unit cell.

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Los Angeles, CA, United States of America

Albert Lee