United Microelectronics Corp.

Albert Kuo Huei Yen

Tsung-Chien Wu

Houshang Aghahassan

Chang-Ching Wu

Chih-Yang Huang

Chung-Che Reed

A layout of a power device is provided. The layout includes a substrate, a unit array, a plurality of first, second, third and fourth signal paths, and a first, second, third and fourth port. The unit array with a plurality of rows is disposed on the substrate. Each row of the unit array includes a plurality of units. The first and second signal paths on the substrate are disposed on a first side and a second side of corresponding odd-numbered rows of the unit array. The third and the fourth signal paths on the substrate are disposed above a corresponding row of the unit array. The first to fourth ports on the substrate are electrically connected to the first to fourth signal paths respectively.

Layout of power device

The invention is directed to a method for manufacturing a metal-insulator-metal transformer together with a capacitor. The method comprises steps of providing a substrate having at least a dielectric layer formed thereon and then forming a first metal layer of the metal-insulator-metal capacitor together with a first metal coil of the transformer over the substrate. An insulating layer is formed to cover the substrate, the first metal layer and the first metal coil. A second metal layer of the metal-insulator-metal capacitor is formed together with a second metal coil of the transformer on the insulating layer.

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San Jose, CA, United States of America

Albert Kuo Huei Yen