International Business Machines Corporation

Globalfoundries Inc.

Albert James Van Norstrand, Jr

Brian William Thompto

Hung Qui Le

Jentje Leenstra

Dung Q Nguyen

Jose Eduardo Moreira

David Allen Hrusecky

Lee Evan Eisen

Bruce Joseph Ronchetti

Sundeep Chadha

Christopher Michael Abernathy

Robert Allen Cordes

David S Levitan

Ronald P Hall

Kurt Alan Feiste

David James Shippy

Steven J Battle

Kenneth Lundy Ward

Brian David Barrick

Susan Elizabeth Eisen

David R Terry

Jonathan James DeMent

Joshua W Bowman

Mehul N Patel

Glenn Owen Kincaid

James Allan Kahle

Richard James Eickemeyer

Phillip G Williams

Maarten Jakob Boersma

David Scott Ray

Salma Ayub

Christopher M Mueller

Akash V Giri

Jennifer L Molnar

Guy L Guthrie

William John Starke

Balaram Sinharoy

Steven R Carlough

Michael Steven Siegel

Naresh Nayar

Peter Juergen Klim

Richard Harold Boivie

Christopher McCall Durham

Geraint M North

Bradly George Frey

William Eric Hall

Sheldon Bernard Levenstein

Christian Zoellin

Elizabeth A McGlone

Daniel Lawrence Stasiak

Cathy May

Guerney D H Hunt

Brian Robert Mestan

Richard William Doing

David Andrew Schroter

James Wilson Bishop

David Mui

Cliff Kucharski

Benjamin Herrenschmidt

Tu-An T Nguyen

Benjamin W Stolt

Michael Lance Karm

Naga P Gorti

Jeffrey Richard Summers

Kevin Neal Magill

Paul Mackerras

Owen Chiang

James Charles Gregerson

Marcy Evelyn Byers

James R Robinson

Bryan Glen Hickerson

Edward J D'Avignon

Milford John Peterson

Kent Li

Paul M Kennedy

Eula Faye Abalos Tolentino

Norman C Chou

Michael A Smoolca

Disclosed is a method for rebalancing blocks of a register file. The method comprises allocating a first set of entries in a first register file to a first hardware thread of a processor core. The method further comprises allocating a second set of entries in a second register file to a second hardware thread of the processor core. The register tags in the first and second register files are compacted such that register tags associated with the first hardware thread are compacted into the first set of entries, and register tags associated with the second hardware thread are compacted into the second set of entries.

Compaction of architected registers in a simultaneous multithreading processor

In an approach to dynamic redistribution of register files, whether a redistribution of register files is necessary is determined. Responsive to determining that the redistribution of register files is necessary, one or more register file transfers that have not yet completed are flushed. One or more register file write locations are allocated for each architected register based on a register free list. Source data is read from each architected register. The source data is written to the one or more register file write locations.

Redistribution of architected states for a processor register file

A simultaneous multithreading processor is configured to select a first thread of the plurality of threads according to a predefined scheme, and access an instruction completion table to determine whether the first thread is eligible to have a first instruction prioritized. Responsive to determining that the first thread is eligible to have the first instruction prioritized, the simultaneous multithreading processor is further configured to execute the first instruction of the first thread using a dedicated prioritization resource.

Prioritized instructions in an instruction completion table of a simultaneous multithreading processor

A processor core having multiple parallel instruction execution slices and coupled to multiple dispatch queues provides flexible and efficient use of internal resources. The configuration of the execution slices is selectable so that capabilities of the processor core can be adjusted according to execution requirements for the instruction streams. A plurality of load-store slices coupled to the execution slices provides access to a plurality of cache slices that partition the lowest level of cache memory among the load-store slices.

Reconfigurable processor with load-store slices supporting reorder and controlling access to cache slices

Techniques are disclosed for performing issue queue snooping for an asynchronous flush and restore of a history buffer (HB) in a processing unit. One technique includes identifying an entry of the HB to restore to a register file in the processing unit. A restore ITAG of the HB entry is sent to the register file via a first restore bus, and restore data of the HB entry and the restore ITAG is sent to the register file via a second restore bus. After the restore ITAG and restore data are sent, an instruction is dispatched before the register file obtains the restore data. After it is determined that the restore data is still available via the second restore bus, a snooping operation is performed to obtain the restore data from the second restore bus for the dispatched instruction.

Issue queue snooping for asynchronous flush and restore of distributed history buffer

Handling unaligned load operations, including: receiving a request to load data stored within a range of addresses; determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice; issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses; executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice; and receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each data communications busses is associated with one of the distinct processor slices.

Handling unaligned load operations in a multi-slice computer processor

Systems, methods, and computer program products are disclosed that control issuing branch instructions in a simultaneous multi-threading (SMT) system. An embodiment system includes an SMT processor circuit that receives, from one of a plurality of threads, a branch instruction having a favor bit. The SMT processor circuit schedules the branch instruction to issue, relative to branch instructions received from other threads in the plurality of threads, based on the favor bit. When the favor bit has a first value, the branch instruction is scheduled to have a higher priority to issue before the branch instructions received from other threads in the plurality of threads. When the favor bit has a second value, the branch instruction is scheduled to issue based an age of the branch instruction relative to respective ages of the branch instructions received from other threads in the plurality of threads.

Most favored branch issue

Variable latency flush filtering including receiving a first flush instruction tag (ITAG) and a second flush ITAG, wherein the first flush ITAG and the second flush ITAG are instructions to invalidate internal operation results after an internal operation identified by the first flush ITAG and the second flush ITAG; determining that the second flush ITAG is before the first flush ITAG by comparing the first flush ITAG and the second flush ITAG; determining that the first flush ITAG requires adjustment; and delaying the flush to a subsequent cycle in response to determining that the second flush ITAG is before the first flush ITAG and determining that the first flush ITAG requires adjustment.

Variable latency flush filtering

Embodiments include systems, methods, and computer program products for using a multi-level history buffer (HB) for a speculative transaction. One method includes after dispatching a first instruction indicating start of the speculative transaction, marking one or more register file (RF) entries as pre-transaction memory (PTM), and after dispatching a second instruction targeting one of the marked RF entries, moving data from the marked RF entry to a first level HB entry and marking the first level HB entry as PTM. The method also includes upon detecting a write back to the first level HB entry, moving data from the first level HB entry to a second level HB entry and marking the second level HB entry as PTM. The method further includes upon determining that the second level HB entry has been completed, moving data from the second level HB entry to a third level HB entry.

Multi-level history buffer for transaction memory in a microprocessor

Blocking instruction fetching in a computer processor, includes: receiving a non-branching instruction to be executed by the computer processor; determining whether executing the non-branching instruction will cause a flush; and responsive to determining that executing the non-branching instruction will cause a flush, disabling instruction fetching for the computer processor for a time, including recoding the instruction such that the recoded instruction will be interpreted by an instruction fetch unit as an unconditional branch instruction.

Blocking instruction fetching in a computer processor

Methods and apparatus for identifying an effective address (EA) using an interrupt instruction tag (ITAG) in a multi-slice processor including receiving, by an instruction fetch unit of the processor, the interrupt ITAG; retrieving an effective address table (EAT) row from an EAT, wherein the EAT row comprises a range of EAs and a first ITAG of a range of ITAGs; accessing a processor instruction vector comprising a plurality of elements, each element corresponding to one of a plurality of ITAGs; applying a mask to the processor instruction vector to obtain a portion of the processor instruction vector that begins with an element corresponding to the first ITAG and is defined by an element corresponding to the interrupt ITAG; calculating an EA offset; and identifying the EA for the interrupt ITAG using the EA offset and the range of EAs in the retrieved EAT row.

Identifying an effective address (EA) using an interrupt instruction tag (ITAG) in a multi-slice processor

Hardware based isolation for secure execution of virtual machines (VMs). At least one virtual machine is executed via operation of a hypervisor and an ultravisor. A first memory component is configured for access by the hypervisor and the ultravisor, and a second memory component is configured for access by the ultravisor and not by the hypervisor. A first mode of operation is operated, such that the virtual machine is executed using the hypervisor, wherein the first memory component is accessible to the virtual machine and the second memory component is not accessible to the virtual machine. A second mode of operation is operated, such that the virtual machine is executed using the ultravisor, wherein the first memory component and the second memory component are accessible to the virtual machine, thereby executing application code and operating system code using the second memory component without code changes.

Hardware based isolation for secure execution of virtual machines

Growing community of inventors

Round Rock, TX, United States of America

Albert James Van Norstrand, Jr