Sperry Corporation

Vlsi Technology, Inc.

Albert J Weidner

William K Hilton

Gary E Schultz

Apparatus for decoding and comparing memory addresses which determines DRAM size and interleave options utilized is disclosed. A row address and bank select bits are decoded and latched and are subsequently compared with the address during the next memory cycle. If the next address matches the address stored in the latch, a 'page hit' occurs and the memory cycle is shortened since the addresses during the consecutive memory address will differ only in the column address.

Page mode comparator decode logic for variable size DRAM types and

An instruction decoding system for data processing apparatus in which alternative instruction interpretations are made possible through hardware sensing of the operational state of one or more machine elements. In one embodiment, a zero detect unit is used to sense the state of a subroutine stack used in a microprogrammed system, therefore permitting a generic 'exit' microcommand to be interpreted either as a 'return' or a 'decode' depending upon the state of the subroutine stack.

Instruction decoding in data processing apparatus

This invention relates to a system for determining an effective address based upon a calculation performed on address information. Depending upon the result of the calculation firmware or hardware will control further operation of the system.

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Tempe, AZ, United States of America

Albert J Weidner