International Business Machines Corporation

Ip-first, LLC

Motorola Corporation

Integrated Device Technology, Inc.

Albert J Loper, Jr

Soummya Mallick

James Allan Kahle

Aubrey Deene Ogden

G Glenn Henry

John Victor Sell

Robert T Golla

Lee Evan Eisen

Marvin A Denman

Bryan P Black

Russell A Reininger

Terry J Parks

Dinesh K Jain

Timothy A Elliott

Michael Putrino

Arturo Martin-de-Nicolas

John L Duncan

Gregory L Limes

A portion of an x86 microprocessor that supports MMX instructions provides a write tracking unit that tracks writes to a separately provided MMX register file, and updates a status register accordingly. A write control unit uses the contents of the status register to control transfers between the MMX register file and the FP register file, so as to only copy those registers that have changed. According to another aspect of the invention, the write control unit insures that architecturally required modifications to the exponent portion of FP registers corresponding to modified MMX registers are provided.

Status register associated with MMX register file for tracking writes

An apparatus and method for tracking coherence between distinct floating point and MMX register files in a microprocessor is provided. The apparatus keeps track of the last time a floating point or MMX instruction was translated and what the instruction type of that previous instruction was by storing the previous instruction type in a register. When the current instruction is translated, the translator compares the current instruction type with the previous instruction type stored in the register to determine if they are different, i.e., if an instruction boundary (a change from MMX to floating point instruction or vice versa) was encountered. If so, the translator generates a signal to indicate that the two register files may be incoherent and need to be made consistent again.

Method and apparatus for tracking coherence of dual floating point and MMX register files

A dual register file MMX-type architecture comprises monitoring logic for identifying which registers in a register file have been written to. The monitoring logic is coupled to write-enable logic associated with each register. Detection logic indicates the occurrence of an instruction boundary event and asserts a signal indicating the possibility of data incoherence between the register files. Control logic coupled to the register files cause a transfer of data between the two register files in response to the asserted signal. The monitoring logic acts in conjunction with the write-enable logic to disable write operations to the receiving registers when the corresponding transferring registers have not been written to.

Method and apparatus for selective writing of incoherent MMX registers

An apparatus and method for improving the execution of floating point instructions in a microprocessor is provided. During decode of a floating point instruction, translation logic generates absolute addresses of specified registers in a floating point register file. These absolute references, as opposed to relative references to a top-of-stack, are inserted into associated micro instructions. In the event of an exception, synchronization logic provides an architected top-of-stack for the floating point instruction associated with the exception to the translation logic so that subsequent instructions will properly reference floating point registers.

Apparatus and method for absolute floating point register addressing

An apparatus and method for performing integer division in a microprocessor are provided. The apparatus includes translation logic, floating point execution logic, and integer execution logic. The translation logic decodes an integer divide instruction into an integer divide micro instruction sequence and an overflow detection micro instruction sequence. The integer divide micro instruction sequence is routed to and executed by the floating point execution logic. The overflow detection micro instruction sequence is routed to and executed by the integer execution logic. The integer execution logic and the floating point execution logic execute the overflow detection micro instruction sequence and the integer divide micro instruction sequence concurrently.

Concurrent execution of divide microinstructions in floating point unit

A microprocessor is provided for executing a floating point exchange micro instruction sequence to swap the contents a first location and a second location. The microprocessor includes register/control logic that receives a floating point micro instruction, determines that the contents of the first location depend upon resolution of a preceding floating point micro instruction, and provides a signal indicating the dependency. The microprocessor also has interlock logic that, in the event of a dependency forwards a new target location to the preceding floating point micro instruction. The microprocessor also includes target location modification logic that receives the new target location and for provides the new target location to the preceding floating point micro instruction. Modification of the target location allows the floating point exchange micro instruction sequence to execute without resolution delay.

Apparatus and method for improved floating point exchange

A method and apparatus for eliminating the setup time typically required for Booth recoding logic is provided. Interlock circuitry detects when a second multiply instruction specifies that the product of a previous multiply instruction is to be used as the multiplier input to the Booth recoding logic. The interlock logic controls mux inputs to both the multiplier path, and the multiplicand path. When the interlock logic detects such a multiplier dependency, the product of the previous multiply instruction is provided to the multiplicand path, and the multiplicand is provided to the multiplier path. The multiplier for the second multiply instruction can therefore be provided to the Booth recoding logic, before the product of the previous multiply instruction is available. The Booth recoding logic is therefore setup, prior to execution of the second multiply instruction.

Method and apparatus for optimizing dependent operand flow within a

A method and device of executing a load multiple instruction in a superscaler microprocessor is provided. The method comprises the steps of dispatching a load multiple instruction to a load/store unit, wherein the load/store unit begins execution of a dispatched load multiple instruction, and wherein the load multiple instruction loads data from memory into a plurality of registers. The method further includes the step of maintaining a table that lists each register of the plurality of registers and that indicates when data has been loaded into each register by the executing load multiple instruction. The method concludes by executing an instruction that is dependent upon source operand data loaded by the load multiple instruction into a register of the plurality of registers indicated by the instruction as a source register, prior to the load multiple instruction completing its execution, when the table indicates the source operand data has been loaded into the source register. Also, according to the present invention, a method of executing a store multiple instruction in a superscaler microprocessor is provided. This method comprises the steps of dispatching a store multiple instruction to a load/store unit, whereupon the load/store unit begins executing the store multiple instruction, wherein the load store instruction stores data from a plurality of registers to memory; and executing a fixed point instruction that is dependent upon data being stored by the store multiple instruction from a register of the plurality of registers indicated by the fixed point instruction as a source register, prior to the store multiple instruction completing its execution, but prohibiting the executing fixed point instruction from writing to a register of the plurality of registers prior to the store multiple instruction completing.

Method and processor that permit concurrent execution of a store

A method and apparatus in a superscalar microprocessor for early completion of floating-point instructions prior to a previous load/store multiple instruction is provided. The microprocessor's load/store execution unit loads or stores data to or from the general purpose registers, and the microprocessor's dispatch unit dispatches instructions to a plurality of execution units, including the load/store execution unit and the floating point execution unit. The method comprises the dispatch unit dispatching a multi-register instruction to the load/store unit to begin execution of the multi-register instruction, wherein the multi-register instruction, such as a store multiple or a load multiple, stores or loads data from more than one of the plurality of general purpose registers to memory, and further, prior to the multi-register instruction finishing execution in the load/store unit, the dispatch unit dispatches a floating-point instruction, which is dependent upon source operand data stored in one or more floating-point registers of the plurality of floating point registers, to the floating-point execution unit, wherein the dispatched floating-point instruction completes execution prior to the multi-register instruction finishing execution.

Processor and method for out-of-order completion of floating-point

A method and system for enhanced system management operations in a superscalar data processing system. Those supervisory level instructions which execute selected privileged operations within protected memory space are first identified as not requiring a full context synchronization. Each time execution of such an instruction is initiated an enable special access (ESA) instruction is executed as an entry point to that instruction or group of instructions. A portion of the machine state register for the data processing system is stored and the machine state register is then modified as follows: a problem bit is set, changing the execution privilege state to 'supervisor;' external interrupts are disabled; and access privilege state bit is set; and, a special access mode bit is set, allowing execution of special instructions. The instructions which execute the selected privileged operations within the protected memory space are then executed. A disable special access (DSA) instruction is then executed which restores the bits within the machine state register which were modified during the ESA instruction. The ESA and DSA instructions are implemented without modifying the instruction stream by utilizing user level procedure calls, thereby reducing the overhead of the branch table necessary to determine the desired execution path.

Method and system for enhanced management operation utilizing intermixed

A method and system for permitting the selective support of non-architected instructions within a superscalar processor system. A special access bit within the system machine state register is provided and set in response to each initiation of an application during which execution of non-architected instructions is desired. Thereafter, each time a non-architected instruction is decoded the status of the special access bit is determined. The non-architected instruction is executed in response to a set state of the special access bit. The illegal instruction program interrupt is issued in response to an attempted execution of a non-architected instruction if the special access bit is not set. In this manner, for example, complex instruction set computing (CISC) instructions may be selectively enabled for execution within a reduced instruction set computing (RISC) data processing system while maintaining full architectural compliance with the reduced instruction set computing (RISC) instructions.

Method and system for selective support of non-architected instructions

A method and system are disclosed for processing instructions within a data processing system including a processor having a plurality of execution units. According to the method of the present invention, a number of instructions stored within a memory within the data processing system are retrieved from memory. A selected instruction among the number of instructions is decoded to determine if the selected instruction would be noneffective if executed by the processor. In a preferred embodiment of the present invention, noneffective instructions include instructions with invalid opcodes and instructions that would not change the value of any data register within the processor. In response to determining that the selected instruction would be noneffective if executed by the processor, the selected instruction is recoded into a specified instruction format prior to dispatching the selected instruction to one of the number of execution units. Detecting noneffective instructions prior to dispatch reduces the decode logic required within the dispatcher and enhances processor performance.

Method and system for recording noneffective instructions within a data

A method and system for efficient memory management in a data processing system which utilizes a memory management unit to translate effective addresses into real addresses within a translation lookaside buffer is disclosed. During a first mode of operation a selected number of effective address identifiers are stored in the translation lookaside buffer. In association with each virtual address identifier is a corresponding real address entry for a single memory block wherein selected virtual addresses may be translated into corresponding real addresses utilizing the translation lookaside buffer. In a second mode of operation, a selected number of virtual address identifiers are stored in a translation lookaside buffer and each virtual address identifier has a number of protection bits stored in association therewith, wherein each protection bit is indicative of a protection status for a large number of contiguous memory blocks beginning with the associated virtual address identifier, wherein memory block protection may be provided for a large number of memory blocks utilizing a fixed size translation lookaside buffer.

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Cedar Park, TX, United States of America

Albert J Loper, Jr