Via Technologies, Inc.

Via Alliance Semiconductor Co., Ltd.

Albert J Loper

Rodney E Hooker

Colin Eddy

Daniel W J Johnson

John Michael Greer

Clinton Thomas Glover

Darius D Gaskins

Douglas Raye Reed

Meera Ramani-Augustin

A processor includes a processing core that detects a predetermined program is running on the processor and looks up a prefetch trait associated with the predetermined program running on the processor, wherein the prefetch trait is either exclusive or shared. The processor also includes a hardware data prefetcher that performs hardware prefetches for the predetermined program using the prefetch trait. Alternatively, the processing core loads each of one or more range registers of the processor with a respective address range in response to detecting that the predetermined program is running on the processor. Each of the one or more address ranges has an associated prefetch trait, wherein the prefetch trait is either exclusive or shared. The hardware data prefetcher performs hardware prefetches for the predetermined program using the prefetch traits associated with the address ranges loaded into the range registers.

Dynamically updating hardware prefetch trait to exclusive or shared at program detection

A hardware data prefetcher is comprised in a memory access agent, wherein the memory access agent is one of a plurality of memory access agents that share a memory. The hardware data prefetcher includes a prefetch trait that is initially either exclusive or shared. The hardware data prefetcher also includes a prefetch module that performs hardware prefetches from a memory block of the shared memory using the prefetch trait. The hardware data prefetcher also includes an update module that performs analysis of accesses to the memory block by the plurality of memory access agents and, based on the analysis, dynamically updates the prefetch trait to either exclusive or shared while the prefetch module performs hardware prefetches from the memory block using the prefetch trait.

Dynamically updating hardware prefetch trait to exclusive or shared in multi-memory access agent system

A fully associative cache memory, comprising: an array of storage elements; an allocation unit that allocates the storage elements in response to memory accesses that miss in the cache memory. Each memory access has an associated memory access type (MAT) of a plurality of predetermined MATs. Each valid storage element of the array has an associated MAT. For each MAT, the allocation unit maintains: a counter that counts of a number of valid storage elements associated with the MAT; and a corresponding threshold. The allocation unit allocates into any of the storage elements in response to a memory access that misses in the cache, unless the counter of the MAT of the memory access has reached the corresponding threshold, in which case the allocation unit replaces one of the valid storage elements associated with the MAT of the memory access.

Fully associative cache memory budgeted by memory access type

A memory subsystem in a microprocessor includes a first-level cache, a second-level cache, and a prefetch cache configured to speculatively prefetch cache lines from a memory external to the microprocessor. The second-level cache and the prefetch cache are configured to allow the same cache line to be simultaneously present in both. If a request by the first-level cache for a cache line hits in both the second-level cache and in the prefetch cache, the prefetch cache invalidates its copy of the cache line and the second-level cache provides the cache line to the first-level cache.

Efficient data prefetching in the presence of load hits

A microprocessor configured to access an external memory includes a first-level cache, a second-level cache, and a bus interface unit (BIU) configured to interface the first-level and second-level caches to a bus used to access the external memory. The BIU is configured to prioritize requests from the first-level cache above requests from the second-level cache. The second-level cache is configured to generate a first request to the BIU to fetch a cache line from the external memory. The second-level cache is also configured to detect that the first-level cache has subsequently generated a second request to the second-level cache for the same cache line. The second-level cache is also configured to request the BIU to refrain from performing a transaction on the bus to fulfill the first request if the BIU has not yet been granted ownership of the bus to fulfill the first request.

A microprocessor is configured to communicate with other agents on a system bus and includes a cache memory and a bus interface unit coupled to the cache memory and to the system bus. The bus interface unit receives from another agent coupled to the system bus a transaction to read data from a memory address, determines whether the cache memory is holding the data at the memory address in an exclusive state (or a shared state in certain configurations), and asserts a hit-modified signal on the system bus and provides the data on the system bus to the other agent when the cache memory is holding the data at the memory address in an exclusive state. Thus, the delay of an access to the system memory by the other agent is avoided.

Avoiding memory access latency by returning hit-modified when holding non-modified data

A BIU prioritizes L1 requests above L2 requests. The L2 generates a first request to the BIU and detects the generation of a snoop request and L1 request to the same cache line. The L2 determines whether a bus transaction to fulfill the first request may be retried and, if so, generates a miss, and otherwise generates a hit. Alternatively, the L2 detects the L1 generated a request to the L2 for the same line and responsively requests the BIU to refrain from performing a transaction on the bus to fulfill the first request if the BIU has not yet been granted the bus. Alternatively, a prefetch cache and the L2 allow the same line to be simultaneously present. If an L1 request hits in both the L2 and in the prefetch cache, the prefetch cache invalidates its copy of the line and the L2 provides the line to the L1.

A method for executing an MMX PSADBW instruction by a microprocessor. The method includes generating packed differences of packed operands of the instruction and generating borrow bits associated with each of the packed differences; for each of the packed differences: determining whether the borrow bit indicates the packed difference is positive or negative and selecting a value in response to the determining, the value comprising the packed difference if the associated borrow bit is positive and a complement of the packed difference if the associated borrow bit is negative; adding the selected values to generate a first sum and a first carry and in parallel adding the borrow bits to generate a second sum and a second carry; adding the first and second sums and the first and second carries to generate a result of the instruction; storing the result in a register of the microprocessor.

Apparatus and method for generating packed sum of absolute differences

A microprocessor for generating a packed sum of absolute differences is disclosed. The microprocessor includes an instruction translator, for translating a Multimedia Extensions (MMX) Packed Sum of Absolute Differences Byte to Word (PSADBW) macroinstruction into at least first and second microinstructions. The microprocessor includes an MMX unit, coupled to the instruction translator, for generating a result of the PSADBW macroinstruction in response to the at least first and second microinstructions.

An apparatus for performing an MultiMedia extension (MMX) Packed Sum of Absolute Differences (PSADBW) instruction is disclosed. The apparatus includes carry-generating subtraction logic that generates packed differences of the subtrahend from the minuend and associated carry bits indicating whether the difference is positive or negative. The apparatus selectively inverts the differences based on the carry bits. Addition logic adds the selectively inverted differences and carry bits substantially in parallel to generate the PSADBW instruction result. In one embodiment, the apparatus also includes two muxes. The first mux selects the selectively inverted differences in the case of a PSADBW instruction and selects a multiply instruction's partial products otherwise. The second mux selects the carry bits in the case of a PSADBW instruction and selects a second multiply instruction's partial products otherwise. The two mux outputs are provided to the addition logic. In one embodiment, the microprocessor translates the PSADBW instruction into at least first and second microinstructions for execution.

A pipeline microprocessor that distributes the instruction dispatching function between a main instruction dispatcher and dispatching logic within a plurality of execution units is disclosed. If the main instruction dispatcher requests load data from a data cache that indicates the data is unavailable, the instruction dispatcher provides to the appropriate execution unit the load instruction (without the load data), a tag (also known by the cache) uniquely identifying the unavailable data, and a false data valid indicator. The cache subsequently obtains the data and outputs it on a bus along with the tag. The dispatching logic in the execution unit is monitoring the bus looking for a valid tag that matches tags of entries in its queue with invalid data indicators. Upon a match, the dispatching logic obtains the data from the bus and subsequently dispatches the instruction along with the data to a functional unit for execution.

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Austin, TX, United States of America

Albert J Loper