International Business Machines Corporation

Siemens Aktiengesellschaft

Albert J Gregoritsch, Jr

Jens G Pohl

Eric Jeffrey White

Ronald R Uttecht

Stephen G Starr

Sheldon C Rieley

Francis E Froebel

Harold W Conru

Ronald Jay Bolam

Russell G Berger, Jr

A method for testing an integrated circuit device includes subjecting the integrated circuit device to an applied magnetic field during the application of one or more test signals, the applied magnetic field inducing magnetostriction effects in one or more materials comprising the integrated circuit device; and determining the existence of any defects within the integrated circuit device attributable to the applied magnetic field.

Method and apparatus for implementing IC device testing with improved SPQL, reliability and yield performance

A semiconductor wafer rework process sideways etches an underlying layer of metal to remove a difficult to etch upper layer of metal without substantially etching that upper layer and without damaging permanent layers of the wafer. If the underlying layer of metal is TiW and the permanent layer is aluminum, the TiW layer can be sideways etched with a hydrogen peroxide and ammonium hydroxide solution that does not damage aluminum lines that are permanently on the wafer. Thus, difficult to remove intermetallic layers, such as tin-copper or chrome-copper, that are located on an underlying layer of TiW, can be successfully removed without danger of damaging permanent aluminum metallization of the wafer.

Rework process

The present invention provides a method for detecting integrated circuit component failures that would normally be triggered during the final card attach step of the manufacturing process. According to the preferred embodiments of the present invention, integrated circuit modules are subjected to an environment that simulates a card attach process step. The process step that simulates the card attach process is introduced into the fabrication process prior to the standard integrated circuit reliability testing procedures, thereby inducing or accelerating failure of certain weak modules and allowing for identification of faulty modules during the subsequent reliability testing steps.

Pre burn-in thermal bump card attach simulation to enhance reliability

According to the present invention, an improved method for locating particle contamination during the integrated circuit manufacturing process is disclosed. The integrated circuit wafer is grounded and then exposed to an electron beam to create an enhanced electrical potential in any conducting or semi-conducting particles embedded in the layered wafer. The embedded particle will begin to accumulate an electrical charge and will reach a certain electrical potential based on the size and composition of the particle as well as the length of exposure to the electron beam. After a sufficient charge has been accumulated in the embedded particle, the wafer is subjected to burn-in testing. Since the particles embedded in the wafer have been previously exposed to the electron beam, the standard voltages applied during burn-in testing will force a certain number of embedded particles to suffer accelerated breakdown. After the defects have occurred and have been located, on-chip fuses can be used to re-route the circuits. As a final step, the wafer is annealed to remove any residual charge in any remaining particle defects not found by the present invention.

Method for charge enhanced defect breakdown to improve yield and

A lead on chip (LOC) semiconductor leadframe package provides notched lead-fingers to eliminate mechanical shear-stress at the peripheral edge of a semiconductor chip. Opposite rows of substantially flat cantilevered lead-fingers are attached by double-sided adhesive tape in thermal contact with the active face of a chip. The lead-fingers are routed in personalized paths over the face of the chip to cover a large surface area to aid heat dissipation. All wirebond connections between the lead-fingers and the chip are made at a centerline connection strip running down the center of the chip. Each of the cantilevered lead-fingers has a notched portion positioned directly over the vulnerable peripheral chip edge to reduce thermal, mechanical shear-stress. Additionally, since corrosion typically follows a lead path, the notch provides increasing path length to prevent corrosive ingress over the chip face.

Personalized area leadframe coining or half etching for reduced

A lead on chip (LOC) semiconductor leadframe package provides notched lead-fingers to eliminate mechanical shear-stress at the peripheral edge of a semiconductor chip. Opposite rows of substantially flat cantilevered lead-fingers are attached by double-sided adhesive tape in thermal contact with the active face of a chip. The lead-fingers are routed in personalized paths over the face of the chip to cover a large surface area to aid heat dissipation. All wirebond connections between the lead-fingers and the chip are made at a centerline connection strip running down the center of the chip. Each of the cantilevered lead-fingers has a notched portion positioned directly over the vulnerable peripheral chip edge to reduce thermal, mechanical shear-stress. Additionally, since corrosion typically follows a lead path, the notch provides an increasing path length to prevent corrosive ingress over the chip face.

Growing community of inventors

South Burlington, VT, United States of America

Albert J Gregoritsch, Jr