Virage Logic Corporation

Albert Harutyunyan

Yervant Zorian

Gevorg Torjyan

Karen Darbinyan

Valery Vardanian

Hayk Chukhajyan

An intellectual property (IP) integrity verification system and method operable with respect to integrating an IP design into a user's embedded IC design. In one embodiment, the IP design is partitioned into a plurality of IP modules based on the requirements of the embedded IC design. For each IP module, a corresponding integrity checker module is provided, wherein each integrity checker module has a port-wise correspondence with its corresponding IP module. The embedded IC design is simulated with the integrity checker modules rather than the IP modules for generating a netlist, which may be verified with respect to any interconnectivity errors associated with the IP modules.

System and method for verifying IP integrity in system-on-chip (SOC) design

Methods and apparatuses in which two or more memories share a processor for Built In Self Test algorithms and features are described. The processor initiates a Built In Self Test for the memories. Each memory has an intelligence wrapper bounding that memory. Each intelligence wrapper contains control logic to decode a command from the processor. Each intelligence wrapper contains logic to execute a set of test vectors on a bounded memory. The processor sends a command based self-test to each intelligence wrapper at a first clock speed and the control logic executes the operations associated with that command at a second clock speed asynchronous with the first speed. The processor loads the command containing representations of a march element and data to one or more of the intelligence wrappers via a serial bus.

Method and apparatus for a command based bist for testing memories

In general, various methods, apparatuses, and systems are described in which logic executes, in series, a plurality of repair algorithms to generate a repair signature for a memory. The memory has a full set of redundant components associated with the memory. At least one or more of the repair algorithms employ a subset of redundant components that contains less than all of the redundant components in the full set when attempting to generate the repair signature.

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Yerevan, Armenia

Albert Harutyunyan