Texas Instruments Corporation

Albert H Taddiken

Han-Tzong Yuan

Donald L Plumton

Jau-Yuann Yang

Hisashi Shichijo

Darrell G Hill

William A White

Lutz J Micheel

Circuits containing resonant tunneling devices are disclosed which offer significant advantages for realizing ultra-dense, ultra-high performance multivalued logic arithmetic integrated circuits. Multivalued logic circuits implemented with resonant tunneling devices can achieve increased speed and density over binary circuits and multiple-valued circuits implemented in conventional IC technologies since multiple binary bits are very efficiently processed by architectures which make use of devices with multiple negative transconductance regions. In one form of the invention, an adder for calculating the sum of two numbers represented by signed digit range-3 base-4 words is constructed from summation circuits,which add corresponding digits of input words X and Y to form digit sums S,, signed range-5 to signed range-3 converter circuits,which use multi-level folding circuits,connected by voltage dividers to decompose the digit sums into an interim sum and carry digit, and a second set of summation circuits,which add interim sum and carry digits to produce the digits of the result. Preferably, the sum is likewise represented by a signed digit range-3 base-4 word. Preferably, the multi-level folding circuits contain resonant tunneling transistors (e.g. bipolar transistors with multiple-peak resonant tunneling diodes,integrated into the emitter).

Multiple resonant tunneling circuits for signed digit multivalued logic operations

A voltage regulator (10) comprising a vertical channel transistor (12). The vertical channel transistor (12) may have a gate (16), a voltage input terminal (18), and a voltage output terminal (20). A reference voltage supply (14) may be coupled to the gate (16).

Integrated voltage regulator circuit with vertical transistor

Multiple resonant tunneling devices offer significant advantages for realizing ultra-dense, ultra-high performance multivalued logic arithmetic integrated circuits. A multivalued logic adder is disclosed, wherein two numbers represented by positive digit base-M range-N words are added by two-input summation circuits 40 which sum corresponding digits, then the digit sums are decomposed into a binary representation by range-7 multivalued to binary converter circuits 42, then three-input summation circuits 44 sum appropriate bits of the binary representations to calculate the digits of a positive digit base-2 range-4 word whose value is the sum of the two numbers. Preferably, the decomposition to binary representation is performed by multi-valued folding circuits 56 which are connected by voltage divider circuitry. Preferably, the multi-valued folding circuits contain multiple-peak resonant tunneling transistors 54. Ripple carries are eliminated and the speed of the adder is independent of input word width.

Reduced complexity multiple resonant tunneling circuits for positive

Multiple resonant tunneling devices offer significant advantages for realizing circuits which efficiently convert values represented by multivalued number systems to conventional binary representation. In one form of the invention, a number represented by a range-4 base-2 word is converted into a conventional binary word (range-2 base-2) having the same value. The conversion is accomplished by a series of decomposition stages 53, each decomposition stage 53 producing an interim range-4 base-2 word and a binary digit, which becomes one of the digits of the binary output word. Preferably, the decomposition at each stage is accomplished by a set of range-4 base-2 to binary converters 50, each of which operates on a single digit of the interim word. Preferably, summation circuits 52 sum outputs of adjoining range-4 base-2 converters 50 to form the new interim word. The least significant digit of the output of the decomposition stage becomes a digit of the output binary word. Preferably, the range-4 base-2 to binary converters 50 are multi-level folding circuits 54 connected by a voltage divider. Preferably, the multi-level folding circuits contain multiple-peak resonant tunneling transistors 56 (e.g. an FET 58 and a multiple-peak resonant tunneling diode 60) which exhibit multiple negative differential transconductance. The novel circuits presented allow the results of multivalued logic operations to be translated to binary representation at very high speed. Additionally, because they make use of resonant tunneling devices, the novel converter circuits described herein may be fabricated with very few components.

Multiple resonant tunneling circuits for positive digit range-4 base-2

A quantizer (20) includes a series of folding amplifiers (22) coupled by a binary weighted resistor ladder (44, 46, 48, 50). Each folding amplifier (22) includes resonant tunneling diodes (34, 36, 38, 40) to control switching of a transistor (32). The output of the folding amplifier (22), as determined by the switching state of the transistor (32), is compared to a reference voltage (V.sub.REF) by a comparator (42). The comparator (42) determines the correct output state of the folding amplifier (22) and generates a digital output signal (V.sub.01) representing a bit of the digital output. The binary weighted resistor ladder successively reduces the input swing received by each folding amplifier to provide fewer and fewer switching transitions at each successive folding amplifier to create the more significant bits of the digital output.

High frequency high resolution quantizer

Generally, and in one form of the invention, an integrated circuit comprising a bipolar transistor and a field effect transistor, wherein a channel of the field effect transistor and a base of the bipolar transistor are formed from a base epitaxial layer 16, and whereby field effect and bipolar transistors are formed within a common material structure is disclosed. In another form of the invention, an integrated circuit comprising a substrate 10, an epitaxial subcollector layer 12, an epitaxial collector layer 14, an epitaxial base layer 16, an epitaxial emitter layer 18, a bipolar transistor formed with an emitter electrical contact 20, 28, 35 to the emitter layer 18, a base contact 34 to the base layer 16, and a collector contact 42 to the subcollector layer 12, and a field effect transistor formed with a first gate contact 20, 30, 39 to the emitter layer 18, a first source contact 36 to the base layer 16, and a first drain contact 37 to the base layer 16, is disclosed.

Method for producing integrated quasi-complementary bipolar transistors

Interface circuits for connecting gallium arsenide circuits with silicon circuits with the interface circuits using a mix of gallium arsenide and silicon devices. Preferred embodiments (200) connect gallium arsenide buffered FET logic circuits (202) with silicon CMOS circuits with a two branch interface circuit under CMOS supply voltages with a BFL logic branch (208-210) merged with a CMOS inverter branch (204-206).

Interface circuit operable to perform level shifting between a first

A programmable resistor 10 is provided having a resistive element 12. Resistive element 12 includes a substrate 26 formed by a layer of semiconductor of a first conductivity-type. A current path 32 is formed in substrate 26 by a layer of semiconductor of a second conductivity-type. An interface 36 having interfacial traps is formed between current path 32 and substrate 26. A backgate 24 is formed adjacent substrate 26. A first switch 14 selectively couples backgate 24 to a first voltage while a second switch 16 selectively couples backgate 24 to a second voltage.

Programmable resistor and an array of the same

A digital memory system of the type which includes an amplifier transistor connected to provide an amplified bit line signal corresponding to the state of a selected memory cell. A bit line pull-up transistor is positioned to function as a bit line current source and as a load device for the amplifier transistor. The amplifier transistor is connected between the pull-up transistor and the bit line and an output node positioned between the pull-up and amplifier transistors provides the amplified bit line signal corresponding to the state of a selected memory cell.

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McKinney, TX, United States of America

Albert H Taddiken