Koninklijke Philips Corporation N.v.

Vlsi Technology, Inc.

Philips Semiconductor, Inc.

Philips Semiconductors of North America Corp.

Albert H Liu

Nelson W White, Ii

Landon B Vines

Mark W Haley

Wing Kei Au

A polisher head backing film that resists slipping relative to a backing plate. In one embodiment, a polisher head backing film/backing plate assembly is provided. The backing film/backing plate assembly includes a backing film with a hole pattern as well as holding pins that protrudes from one of the film's surfaces. The backing film/backing plate assembly also includes a backing plate that has a corresponding hole pattern and receiving holes such that the hole patterns on the backing film and backing plate can be aligned. The receiving holes can receive the holding pins of the backing film such that when the hole patterns are aligned, the holding pins and the receiving holes are also aligned. The holding pins can thus be inserted into the receiving holes upon alignment such that the backing film is prevented from moving relative to the backing plate once the holding pins are properly inserted.

Non-slip polisher head backing film

A method for making reliable interconnect structures on a semiconductor substrate having a first dielectric layer is disclosed. The method includes depositing a glue layer of TiN followed by tungsten chemical vapor deposition after the contact or via is defined in the dielectric. Then, tungsten etchback or Chemical Mechanical Polishing (CMP) is performed to remove the tungsten and TiN over the dielectric surface with slight dishing of the tungsten within the plug. Next, a blanket deposition of Copper by electrochemical deposition is performed and Copper CMP is used to remove the copper from the dielectric surface while maintaining a coating of copper over the tungsten in the plug. Then, metal stack deposition, patterning and metal etching is performed and a barrier layer of silicon nitride is presented to minimize the copper diffusion. Finally, a deposition of an Interlevel Dielectric (ILD) is deposited. The deposition of a protective material such as copper above the tungsten in the plug blocks the dissolution pathway of tungsten in the highly alkaline post metal etch strip solvent. Copper is used as an example due to its favorable characteristic of being deposited and polished commercially, and the relatively low volatility of etch products (CuCl or CuCl ) during the metal etch whereas Cl /BCl is the typical etch chemistry employed in semiconductor manufacturing. The deposition of silicon nitride after metal etch is essential to minimize the out-diffusion of copper into upper level dielectrics whereas the TiN glue layer minimizes the copper diffusion from the side of the vias or the contact.

System and method for preventing electrochemical erosion by depositing a protective film

A method of conditioning a polish pad at the point of polish and for dispensing slurry at the point of polish. In one embodiment, the method comprises several steps. In the first step, polishing slurry is received at a CMP machine. Next, a polish pad is rotated. Then, the polishing slurry is dispensed onto a portion of said polish pad located proximately around a location designated for holding a wafer.

Method and apparatus for conditioning a polish pad at the point of polish and for dispensing slurry at the point of polish

According to an example embodiment, the present invention comprises a CMP pad conditioner arrangement. An inlet is configured and arranged for receiving treatment elements. A distribution surface is coupled to the inlet and is configured and arranged to disperse the treatment elements. A multitude of outlets are coupled to the distribution surface and are configured and arranged to dispense the treatment elements onto a CMP pad. Benefits of using this embodiment include enhanced pad cleaning, better slurry dispense, improved wafer quality, and faster production.

CMP pad conditioner arrangement and method therefor

A semiconductor fabrication process uses a buried, oxygen-rich layer as a stop etch in a trench isolation area, with minimal masking. According to one embodiment, the process involves applying a mask to protect selected portions of a silicon-based substrate, and then using the mask to implant an oxygen-based substance into unmasked portions of the substrate, thereby forming a buried oxygen layer at a selected depth within the substrate. The same mask is then used in an etching process to form the desired trench structure. The depth of the trench is defined as a result of terminating the etch process upon reaching the buried oxygen layer.

Semiconductor having self-aligned, buried etch stop for trench and

An electrostatic chuck device for clamping a semiconductor wafer substrate during processing of the semiconductor wafer includes a power source, at least one negative pole, and a plurality of positive poles. Each positive pole selected from the plurality of positive poles is electrically separated from the negative pole. Also provided is a plurality of fuses, each fuse of the plurality of fuses is coupled to an associated positive pole included in the plurality of positive poles. Each fuse is further coupled to the power source. In some embodiments, each positive pole is electrically separated from the negative pole by an insulating epoxy. In other embodiments, the plurality of positive poles are connected to each other in parallel.

Growing community of inventors

San Antonio, TX, United States of America

Albert H Liu