Hewlett-packard Development Company, L.p.

Compaq Computer Corporation, Inc.

Albert H Chang

Christopher Garza

Ryan A Callison

James R Reif

Thomas W Grieff

Kevin B Leigh

William C Galloway

Michael Lawrence Sabotta

Mark J Thompson

Jeff M Carlson

Hubert Brinkman

A method comprises obtaining connectivity information from a plurality of electrical devices. Each such electrical device is separately coupled to a backplane, and at least one electrical device comprises a plurality of electrical interfaces adapted to be selectively coupled to each of multiple other electrical devices. Based on connectivity information from the at least one electrical device, the method further comprises providing configuration information to the at least one electrical device to cause the at least one electrical device to electrically couple to a target other electrical device via the backplane.

Configurable backplane connectivity for an electrical device

A multi-port adapter and method of operation suitable for use with serial ATA devices is disclosed. An adapter includes a switch that receives input from multiple host devices and an arbiter module for assigning a priority scheme to received commands. An outstanding request table is implemented as a memory module for storing identifying information associated with commands received from multiple host devices, and a free pointers queue is maintained to track slots available in the outstanding request table. A command tracker state machine decodes incoming requests from hosts, monitors the execution by these commands by the ATA device, and updates the memory module to reflect completion of commands. Also disclosed is a storage system including an adapter of the present invention and ATA storage devices.

System and method for providing multi-initiator capability to an ATA drive

A single read request to a memory controller generates multiple read actions along with XOR/DATUM manipulation of that read data. Fewer memory transfers are required to accomplish a RAID/DATUM parity update. This allows for higher system performance when memory bandwidth is the limiting system component. In implementation, a read buffer with XOR capability is tightly coupled to a memory controller. New parity does not need to be stored in the controller's memory. Instead, a memory read initiates multiple reads from memory based on an address decode. The data from the reads are multiplied and XOR'd before being returned to the requestor. In the case of a PCI-X requestor, this occurs as a split-completion.

Memory controller interface with XOR operations on memory read to accelerate RAID operations

A memory interface controller employs a DATUM multiplier within a destination address to perform DATUM RAID operations. If destination data is in an XOR memory address space, then the multiplier can indicate to multiply source data by the multiplier and XOR that resulting data with the destination data. The DATUM multiplier can be read in response to detection of a memory command. The multiplier alternatively can be used in connection with an input/output bus write command to write source data from the input/output address space to an XOR memory address space. In response to such a write command, the input/output bus data in the input/output address space is multiplied by the multiplier; that resulting data is XORed with the destination data in the XOR memory address space. The multiplier in this case can be within an input/output bus address associated within the input/output bus data.

Memory interface controller for datum raid operations with a datum multiplier

A memory interface controller includes a read buffer to pipeline data from a synchronous dynamic random access memory (DRAM) in response to a plurality of consecutive SDRAM burst read requests, a write buffer to store write data, an exclusive or (XOR) engine to XOR the write data with the data from the read buffer, and a write interface to write resulting data from XORing the write data and the data from the read buffer to the synchronous DRAM. Data is pipelined in the read buffer by repeatedly issuing an SDRAM burst read request before data is transferred out of the synchronous DRAM in response to a previous SDRAM burst read request until a desired amount of data is stored in the read buffer. The memory interface controller thus can perform an external read-modify-write cycle for the synchronous DRAM. The synchronous DRAM can serve as a RAID (Redundant Array s of Inexpensive Disks) memory.

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Houston, TX, United States of America

Albert H Chang