International Business Machines Corporation

Albert Frisch

Juergen Pille

Dieter F Wendel

Rolf Sautter

Tobias Werner

Philipp Salz

Thomas Kalla

Markus Brink

Harry S Barowski

An embodiment of a qubit tuning device includes a first layer configured to generate a magnetic field, the first layer comprising a material exhibiting superconductivity in a cryogenic temperature range. In an embodiment, the qubit tuning device includes a qubit of a quantum processor chip, wherein the first layer is configured to magnetically interact with the qubit such that a first magnetic flux of the first layer causes a first change in a first resonance frequency of the qubit by a first frequency shift value.

Qubit tuning by magnetic fields in superconductors

An embodiment may include an integrated circuit. The integrated circuit may include a plurality of vertical transistor structures arranged in a two-dimensional grid pattern including a longitudinal set of grid-lines, a transversal set of grid-lines, and nodes at each intersection of the longitudinal set of grid-lines and the transversal set of grid-lines. Each vertical transistor structure is arranged substantially perpendicular to the plurality of layers of the integrated circuit and aligned with each node of the two-dimensional grid pattern.

Integrated circuit with vertical structures on nodes of a grid

An embodiment may include a method of forming a microelectronic device. The method may include forming a pair of transistors stacked vertically and connected in series, each of the pair of transistors are of the same type. The method may include forming a memory element including a first inverter containing a first inverter transistor and an access transistor. The first inverter transistor is connected to a power supply rail. The access transistor is connected to a bitline. The first inverter transistor is a first transistor of the pair of vertically stacked transistors and the access transistor is a second transistor of the pair of vertically stacked transistors. The pair of transistors are arranged substantially perpendicular to the plurality of layers.

Microelectronic device with a memory element utilizing stacked vertical devices

An embodiment may include a method of forming an integrated circuit. The method may include forming a first pair of transistors stacked vertically above a semiconductor substrate arranged substantially perpendicular to the plurality of layers. Each of the first pair of vertically stacked transistors are of the same type and are connected in series. The method may include forming a second pair of transistors connected in parallel and arranged substantially perpendicular to the plurality of layers. The second pair of transistors are a different type than the first pair of vertically stacked transistors. The method may include forming a power supply rail within the semiconductor substrate and arranged at one end of the first pair of vertically stacked transistors.

Buried conductive layer supplying digital circuits

An embodiment may include a microelectronic device. The microelectronic device may include a first pair of transistors stacked vertically and connected in series. Each of the first pair of transistors are of the same type. The microelectronic device may include a second pair of transistors connected in parallel. The second pair of transistors being a different type than the first pair of transistors. The first pair of transistors and the second pair of transistors are arranged substantially perpendicular to the plurality of layers.

Microelectronic device utilizing stacked vertical devices

Generating design data for manufacturing a logic array of a semiconductor circuit from specification data describing the logic array. The specification is transformed into structured specification data including objects corresponding to circuit cells of a first type and logic specification data specifying the logic circuitry to be included in the logic array, and into structure data including placing and routing information concerning the circuit cells of the first type. A determination is made of circuit cells of a second type from the logic specification data. The circuit cells of the first type are pre-placed and routed based on the structure data. The circuit cells of second type are automatically placed and routed.

Growing community of inventors

Stuttgart, Germany

Albert Frisch