Intel Corporation

Other

Albert Fazio

Gregory E Atwood

Mark E Bauer

James Q Mi

Kerry Dean Tedrow

Neal R Mielke

Johnny Javanifard

Derchang Kau

Paul D Ruby

James Brennan, Jr

Stephen N Keeney

Krishna Kumar Parat

Jawad Basit Khan

Rajesh Sundaram

Shekoufeh Qawami

Richard L Coulson

Jahanshir J Javanifard

Sanjay S Talreja

Yudong Kim

Robert E Larsen

Been-Jon K Woo

Glen N Wada

Kevin W Frary

Rex Stone

James O Mi

Martin Langhammer

Valluri Ramana Rao

Mahesh A Iyer

Steven E Wells

Robert N Hasbun

Ravi Prakash Gutala

Scott J Weber

Aravind Raghavendra Dasu

Prashant S Damle

Ilya K Ganusov

Mamun Ur Rashid

Greg Atwood

Phillip M Kwong

Alan E Baker

Stefan K Lai

Marc E Landgraf

Kenneth E Wojciechowski

Matthew I Adiletta

Mark J Christopherson

Krishnamurthy Murali

Wei Fang

Chakravarthy Yarlagadda

Richard A Lodenquai

Kenneth Woiciechowski

Mike Brown

Ken Wojciechowski

Terence Magee

Glen Wada

A three dimensional circuit system includes a first integrated circuit die having a core logic region that has first memory circuits and logic circuits. The three dimensional circuit system includes a second integrated circuit die that has second memory circuits. The first and second integrated circuit dies are coupled together in a vertically stacked configuration. The three dimensional circuit system includes third memory circuits coupled to the first integrated circuit die. The third memory circuits reside in a plane of the first integrated circuit die. The logic circuits are coupled to access the first, second, and third memory circuits and data can move between the first, second, and third memories. The third memory circuits have a larger memory capacity and a smaller memory access bandwidth than the second memory circuits. The second memory circuits have a larger memory capacity and a smaller memory access bandwidth than the first memory circuits.

Three dimensional circuit systems and methods having memory hierarchies

Cross point memory architectures, devices, systems, and methods are disclosed and described, and can include a cross point memory core subsystem having increased bandwidth that is scalable. The memory core can include a plurality of independently operating partitions, each comprising a plurality of cross point memory arrays.

Scalable bandwidth non-volatile memory

A memory device includes a memory array having multiple nonvolatile memory cells that stores data as a set or a reset state of the memory cells. The nonvolatile memory cells can be resistance-based memory, which stores data based on resistive state of the memory cells. A controller coupled to the memory array periodically samples set and reset margins for memory cells of the memory array. Responsive to detection of a change in a margin, the system can adaptively adjust a preset electrical setting used to differentiate between a set state and a reset state.

Memory preset adjustment based on adaptive calibration

Techniques for determining access information describing an accessing of a phase change memory (PCM) device. In an embodiment, an initial read time for a PCM cell is determined based on a final read time for the PCM cell, set threshold voltage information and a reset threshold voltage drift, wherein the final read time and the initial read time define a time window for reading the PCM cell. In another embodiment, a time window extension is determined based on a reset threshold voltage drift.

Method, apparatus and system to determine access information for a phase change memory

When an error correction code (ECC) unit finds uncorrectable errors in a solid state non-volatile memory device, a process may be used in an attempt to locate and correct the errors. This process may first identify 'low confidence' memory cells that are likely to contain errors, and then determine what data is more likely to be correct in those cells, based on various criteria. The new data may then be checked with the ECC unit to verify that it is sufficiently correct for the ECC unit to correct any remaining errors.

Data error recovery in non-volatile memory

According to an embodiment of the invention, a flash memory cell includes a first gate stack and a second gate stack having a film deposited across the gap between the first and second gate stacks so that the film creates a void between the first and second gate stacks. Dielectric materials may be used to reduce conductivity between the two stacks. A dielectric material that is resistant to conductivity has a low dielectric constant (k). The lowest-k dielectric material is air, which has a dielectric constant of approximately 1. By creating a void between the two gate stacks, the least conductive material (air) is left filling the space between the gate stacks, and the likelihood of parasitic coupling of two adjacent floating gates is substantially reduced.

Flash memory cell having reduced floating gate to floating gate coupling

A method for determining data stored by a memory cell. The memory cell has a select gate coupled to a wordline, a first electrode coupled to a bitline, and a second electrode coupled to a conductor. The method comprises: floating the bitline; applying a first voltage to the wordline; applying a second voltage to the conductor such that the bitline is set to a third voltage that is equal to the first voltage minus a threshold voltage of the memory cell; and sensing the third voltage to determine the data stored by the memory cell.

Flash memory device of capable of sensing a threshold voltage of memory cells on a page mode of operation

Briefly, in accordance with one embodiment of the invention, a memory device may include a memory layer and a MEMS layer. The memory layer may include an integrated circuit with a multiplexer and optionally a memory controller and a storage medium disposed on the integrated circuit where the storage medium includes chalcogenide islands as storage elements. The MEMS layer may include a movable MEMS platform having probes to connect selected chalcogenide islands via positioning of the MEMS platform. A high voltage source disposed external to the memory layer and the MEMS layer may provide a high voltage to a stator electrode on the memory layer and to a rotor electrode on the MEMS platform to control movement of the MEMS platform with respect to the storage medium. The memory device may be utilized in portable electronic devices such as media players and cellular telephones to provide a nonvolatile storage of information.

MEMS probe based memory

A nonvolatile memory cell comprising a pair of spaced apart shallow trench isolation regions formed in a substrate and defining a substrate active region. A tunnel dielectric is formed on the substrate active region. A floating gate is formed on the tunnel dielectric and is self aligned between the spaced apart shallow trench isolation regions. A dielectric layer is formed on the floating gate and a control gate formed on the dielectric layer. A source region and a drain region are formed in the substrate active region on opposite sides of the floating gate.

Integrated memory cell and method of fabrication

A method and circuitry for programming a memory cell to one of at least three amounts of charge. The amount of charge placed in the memory cell is increased by increasing the voltage level of a programming pulse applied to the memory cell.

Method and circuitry for storing discrete amounts of charge in a single

Methods and apparatus for determining the state of a memory cell having more than two possible states are disclosed. For a first embodiment, the state of a flash cell having n states, where n is a power of 2, is determined by selectively comparing the threshold voltage V.sub.t of a selected memory cell to (n-1) reference voltages. For every two states, a single comparator is provided such that the total number of comparators is equal to the number of bits stored in the memory cell.

Sensing scheme for flash memory with multilevel cells

Growing community of inventors

Los Gatos, CA, United States of America

Albert Fazio