Analog Devices Global

Analog Devices,inc.

Analog Devices International Unlimited Company

Albert C O'Grady

Javier Alejandro Salcedo

Alan J O'Donnell

Patrick Martin McGuinness

David J Clarke

David Aherne

John Anthony Cleary

Donal P Geraghty

Colm F Slattery

Colin Gerard Lyden

John M Wynne

Denis Martin O'Connor

Tudor M Vinereanu

Patrick C Kirby

Michal Brychta

Aidan J Cahalane

Michael Collins

Valerie Hamilton

James F Caffrey

Sean Smith

Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.

Charge storage with electrical overstress protection

Storing charge associated with electrical overstress

Electrical overstress reporting

Systems for monitoring or control can include reconfigurable input and output channels. Such reconfigurable channels can include as few as a single terminal and a ground pin, or such channels can include three or four terminal configuration such as for use in four-terminal resistance measurements. Channel reconfiguration can be accomplished such as using software-enabled or firmware-enabled control of channel hardware. Such channel hardware can include analog-to-digital and digital-to-analog conversion capability, including use of a digital-to-analog converter to provide field power or biasing. In an example, the interface circuit can provide a selectable impedance.

Configurable hardware platform for measurement or control

Electrical overstress recording and/or harvesting

A single chip integrated circuit measuring circuit () for determining a characteristic of the impedance of an external complex impedance circuit () for facilitating characterization of the impedance of the complex impedance circuit () comprises a signal generating circuit () for generating a variable frequency stimulus signal for applying to the complex impedance circuit (). A first receiving circuit () receives a response signal from the complex impedance circuit () in response to the stimulus signal and conditions the response signal. A first analog-to-digital converter () converts the conditioned response signal to a first digital output signal, which is read from the first analog-to-digital converter () through a first digital output port (). The response signal from the complex impedance circuit () is a current signal, and a current to voltage converter circuit () converts the response signal to a voltage signal. A first RMS to DC level converting circuit () converts the AC voltage of the response signal to a DC voltage level, and a fourth multiplexer () selectively applies the voltage response signal or the DC voltage level signal to the first analog-to-digital converter (), depending on whether it is desired that the first digital output signal should be indicative of the phase shift or amplitude change in the response signal relative to the stimulus signal. A second receiving circuit () receives the stimulus signal, and similarly converts the stimulus signal to a second digital output signal for facilitating comparison of the response signal with the stimulus signal.

Measuring circuit and a method for determining a characteristic of the impedance of a complex impedance element for facilitating characterization of the impedance thereof

A multi-channel circuit () comprising a plurality of on-chip channels (CHto CH), each of which comprises a DAC () for converting digital data into analogue output signals independently of each other under the control of an interface and control logic circuit (). The analogue output signals from the DACs () are outputted on output terminals () of the respective channels (CHto CH). The digital input data and control and address signals for controlling the conversion of the digital data in the DACs () are inputted to the interface and control logic circuit () through an I/O port (). DAC registers () are provided in the respective channels (CHto CH) for storing the digital words to be converted in the corresponding DACs (). Analogue input terminals () are provided for receiving analogue input signals (), for example, analogue signals from external systems which may be controlled by the output signals from the DACs (). A multiplexer () is operable under the control of the interface and control logic circuit () for selectively and sequentially applying the analogue output signals from the DACs () and the analogue input signals from the analogue input terminals () to a monitoring output terminal () for facilitating independent monitoring of the analogue output signals from the DACs (), and the analogue inputs on the analogue input terminals ().

Multi-channel integrated circuit comprising a plurality of DACs, and a method for monitoring the output of the DACs

A signal generator () for generating a square waveform analog voltage output signal comprises an on-chip DAC () which outputs the analog voltage signal on an output terminal (). On-chip first and second programmable registers () store first and second digital words which correspond to the maximum and minimum voltage values of the analog output signal. An on-chip switch circuit () selectively and alternately switches the first and second registers () to an on-chip DAC register () from which the respective first and second digital words are loaded into the DAC () in response to a load DAC signal generated by a control circuit (). The load DAC signal is generated in response to an externally generated LDAC signal in the form of a clock signal which is applied to an LDAC terminal (). A flip-flop () in response to the load DAC signal outputs a control signal on a control line () for alternately switching the first and second registers () to the DAC register (). The frequency of the analog output signal is determined by the frequency of the LDAC signal, and is half the frequency of the LDAC signal.

Signal generation using DAC having selectively switched registers storing output values

Growing community of inventors

Mungret, Ireland

Albert C O'Grady