Google Inc.

Exaflop LLC

Albert Borchers

Robert S Sprinkle

Andrew Swing

Jason W Klaus

Joel Dylan Coburn

Christopher Lyle Johnson

Thomas James Norrie

Benjamin Charles Serebrin

Ken Krieger

Monish Shah

Benjamin Steel Gelb

Grant Grundler

Justin Kennington

Andrews T Swing

IOMMU map-in may be overlapped with second tier memory access, such that the two operations are at least partially performed at the same time. For example, when a second tier memory read into a storage device controller internal buffer is initiated, an IOMMU mapping may be built simultaneously. To achieve this overlap, a two-stage command buffer is used. In a first stage, content is read from a second tier memory address into the storage device controller internal buffer. In a second stage, the internal buffer is written into the DRAM physical address.

Two stage command buffers to overlap IOMMU map and second tier memory reads

Methods, systems, and apparatus for determining whether an access bit is set for each page table entry of a page table based on a scan of the page table with at least one page table walker, the access bit indicating whether a page associated with the page table entry was accessed in a last scan period; incrementing a count for each page in response to determining that the access bit is set for the page table entry associated with the page; resetting the access bit after determining whether the access bit is set for each page table entry; receiving a request to access, from a main memory, a first page of data; initiating a page fault based on determining that the first page of data is not stored in the main memory; and servicing the page fault with a DMA engine.

Hybrid memory management

Methods, systems, and apparatus for receiving a request to access, from a main memory, data contained in a first portion of a first page of data, the first page of data having a first page size; initiating a page fault based on determining that the first page of data is not stored in the main memory; allocating a portion of the main memory equivalent to the first page size; transferring the first portion of the first page of data from the secondary memory to the allocated portion of the main memory without transferring the entire first page of data; and updating a first page table entry associated with the first portion of the first page of data to point to a location of the allocated portion of the main memory to which the first portion of the first page of data is transferred.

Memory management supporting huge pages

A method includes deploying non-volatile random access memory (NVRAM) coupled to a processor or central processing unit (CPU) core of a computing device as a peripheral device via an input/output (I/O) bus, and providing a NVRAM application programming interface (API) for the CPU core to conduct NVRAM read and write operations. Providing the NVRAM API includes allocating a single memory buffer per command to hold data transferred to or from the NVRAM. The method includes configuring the processor in conjunction with the NVRAM API to set up command queues inside in the host Memory Mapped Input Output (MMIO) space.

Non-volatile memory device application programming interface

Methods, systems, and apparatus for receiving a request to access, from a main memory, a first cache line of a page of data; determining that the first cache line is not stored in the main memory and is stored in a secondary memory, and in response: transferring the first cache line of the page of data from the secondary memory to the main memory without transferring the entire page of data, wherein a remaining portion of the page of data remains stored in the secondary memory; updating a page table entry associated with the page of data to point to a location of the page of data in the main memory; and transferring the remaining portion of the page of data from the secondary memory to the main memory.

A data storage device includes multiple flash memory devices with each of the flash memory devices being arranged into multiple blocks having multiple pages for storing data. The data storage device includes a memory controller operationally coupled with the flash memory devices. The memory controller is configured to mark one or more of the pages of the flash memory devices as available for deletion and maintain the marked pages as available for being read until deleted during garbage collection.

Data management in a data storage device

A data storage device may include an interface that is arranged and configured to interface with a host, a command bus, multiple memory devices that are operably coupled to the command bus and a controller that is operably coupled to the interface and to the command bus. The controller may be arranged and configured to receive a read metadata command for a specified one of the memory devices from the host using the interface, read metadata from the specified memory device and communicate the metadata to the host using the interface.

Data storage device with copy command

A data storage device includes multiple flash memory devices, where each of the flash memory devices is arranged into multiple blocks having multiple pages for storing data. The data storage device includes a memory controller operationally coupled with the flash memory devices. The memory controller is configured to receive a logical to physical address translation map from a host device, where a physical address includes a physical address for one of the flash memory devices. The memory controller is configured to store the logical to physical address translation map in a memory module on the memory controller, receive read commands directly from an application running on the host device, where the read commands include logical memory addresses that refer to the logical locations on the flash memory devices, and translate the logical addresses to physical memory addresses using the logical to physical address translation map.

Using a logical to physical map for direct user space communication with a data storage device

A data storage device includes multiple flash memory devices, where each of the flash memory devices are arranged into multiple blocks having multiple pages for storing data. The data storage device includes a memory controller that is operationally coupled with the flash memory devices. The memory controller is configured to receive a virtual to physical memory address translation map from a host device, where a physical memory address includes a physical address for memory on the host device. The memory controller is configured to store the virtual to physical memory address translation map in a memory module on the memory controller, receive commands directly from an application running on the host device, where the commands include virtual memory addresses that refer to the memory on the host device and translate the virtual memory addresses to physical memory addresses using the virtual to physical memory address translation map.

Using a virtual to physical map for direct user space communication with a data storage device

A system is described that includes a power conversion module, a data port, a controller to receive data from the data port, and a data store containing instructions that when executed by the controller perform operations to control the power conversion module. The operations include executing instructions in a first portion of the data store during booting of the controller, executing instructions in a second portion of the data store after the controller has booted, receiving a signal from the data port indicating the instructions in the second portion are to be modified, receiving from the data port modified instructions to be stored in the second portion, and executing, in response to the signal, the instructions in the first portion to store the modified instructions in the second portion.

Controlling access to a power supply memory

A method of partitioning a data storage device that has a plurality of memory chips includes determining a number memory chips in the data storage device, defining, via a host coupled to the data storage device, a first partition of the data storage device, where the first partition includes a first subset of the plurality of memory chips, defining a second partition of the data storage device via the host where the second partition includes a second subset of the plurality of memory chips, such that the first subset does not include any memory chips of the second subset and wherein the second subset does not include any memory chips of the first subset.

Growing community of inventors

Santa Cruz, CA, United States of America

Albert Borchers